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lm3s600 microcontroller da t a sheet copyright ? 2007 luminary micro, inc. ds-lm3s600-1728 preliminar y
legal disclaimers and t rademark information informa tion in this document is provided in connection with luminar y micro products. no license, express or implied, by est oppel or other wise, t o any intellectual proper ty rights is granted by this document . except as provided in luminar y micro's terms and conditions of sale for such products, luminar y micro assumes no liability wha tsoever, and luminar y micro disclaims any express or implied w arranty , rela ting t o sale and/or use of luminar y micro's products including liability or w arranties rela ting t o fitness for a p ar ticular purpose, merchant ability , or infringement of any p a tent , copyright or other intellectual proper ty right . luminar y micro's products are not intended for use in medical, life sa ving, or life-sust aining applica tions. luminary micro may make changes to specifcations and product descriptions at any time, without notice. contact your local luminary micro sales offce or your distributor to obtain the latest specifcations before placing your product order . designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefned." luminary micro reserves these for future defnition and shall have no responsibility whatsoever for conficts or incompatibilities arising from future changes to them. copyright ? 2007 luminary micro, inc. all rights reserved. stellaris is a registered trademark and luminary micro and the luminary micro logo are trademarks of luminary micro, inc. or its subsidiaries in the united states and other countries. arm and thumb are registered trademarks and cortex is a trademark of arm limited. other names and brands may be claimed as the property of others. luminary micro, inc. 108 w ild basin, suite 350 austin, tx 78746 main: +1-512-279-8800 fax: +1-512-279-8879 http://www .luminarymicro.com october 01, 2007 2 preliminary
t able of contents about this document .................................................................................................................... 15 audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 about this manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 related documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1 architectural overview ...................................................................................................... 17 1.1 product features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.2 t arget applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.3 high-level block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.4 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.4.1 arm cortex?-m3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.4.2 motor control peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.4.3 analog peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.4.4 serial communications peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.4.5 system peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.4.6 memory peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.4.7 additional features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.4.8 hardware details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2 arm cortex-m3 processor core ...................................................................................... 28 2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2.1 serial wire and jt ag debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2.2 embedded t race macrocell (etm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2.3 t race port interface unit (tpiu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2.4 rom t able . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2.5 memory protection unit (mpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2.6 nested v ectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3 memory map ....................................................................................................................... 34 4 interrupts ............................................................................................................................ 36 5 jt ag interface .................................................................................................................... 38 5.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.2.1 jt ag interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.2.2 jt ag t ap controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.2.3 shift registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.2.4 operational considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.3 initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.4 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.4.1 instruction register (ir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.4.2 data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6 system control ................................................................................................................... 48 6.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.1 device identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.2 reset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3 october 01, 2007 preliminary lm3s600 microcontroller
6.1.3 power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.1.4 clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.1.5 system control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.2 initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.3 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.4 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7 internal memory ............................................................................................................... 103 7.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.2.1 sram memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.2.2 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 7.3 flash memory initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 7.3.1 changing flash protection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 7.3.2 flash programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 7.4 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 7.5 flash register descriptions (flash control of fset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 7.6 flash register descriptions (system control of fset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8 general-purpose input/outputs (gpios) ....................................................................... 119 8.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 8.1.1 data control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 8.1.2 interrupt control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 8.1.3 mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 8.1.4 pad control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 8.1.5 identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 8.2 initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 8.3 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 8.4 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 9 general-purpose t imers ................................................................................................. 157 9.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 9.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 9.2.1 gptm reset conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 9.2.2 32-bit t imer operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 9.2.3 16-bit t imer operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 9.3 initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 9.3.1 32-bit one-shot/periodic t imer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 9.3.2 32-bit real-t ime clock (r tc) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 9.3.3 16-bit one-shot/periodic t imer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 9.3.4 16-bit input edge count mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 9.3.5 16-bit input edge t iming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 9.3.6 16-bit pwm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 9.4 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 9.5 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 10 w atchdog t imer ............................................................................................................... 193 10.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 10.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 10.3 initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 10.4 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 october 01, 2007 4 preliminary t able of contents
10.5 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 1 1 universal asynchronous receivers/t ransmitters (uart s) ......................................... 216 1 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 1 1.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 1 1.2.1 t ransmit/receive logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 1 1.2.2 baud-rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 1 1.2.3 data t ransmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 1 1.2.4 fifo operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 1 1.2.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 1 1.2.6 loopback operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 1 1.3 initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 1 1.4 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 1 1.5 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 12 synchronous serial interface (ssi) ................................................................................ 254 12.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 12.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 12.2.1 bit rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 12.2.2 fifo operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 12.2.3 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 12.2.4 frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 12.3 initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 12.4 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 12.5 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 13 inter-integrated circuit (i 2 c) interface ............................................................................ 291 13.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 13.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 13.2.1 i 2 c bus functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 13.2.2 a vailable speed modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 13.2.3 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 13.2.4 loopback operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 13.2.5 command sequence flow charts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 13.3 initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 13.4 i 2 c register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 13.5 register descriptions (i 2 c master) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 13.6 register descriptions (i2c slave) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 14 analog comparators ....................................................................................................... 326 14.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 14.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 14.2.1 internal reference programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 14.3 initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 14.4 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 14.5 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 5 october 01, 2007 preliminary lm3s600 microcontroller
15 pin diagram ...................................................................................................................... 339 16 signal t ables .................................................................................................................... 340 17 operating characteristics ............................................................................................... 347 18 electrical characteristics ................................................................................................ 348 18.1 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 18.1.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 18.1.2 recommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 18.1.3 on-chip low drop-out (ldo) regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 18.1.4 power specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 18.1.5 flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 18.2 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 18.2.1 load conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 18.2.2 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 18.2.3 analog comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 18.2.4 i 2 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 18.2.5 synchronous serial interface (ssi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 18.2.6 jt ag and boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 18.2.7 general-purpose i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 18.2.8 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 19 package information ........................................................................................................ 358 a serial flash loader .......................................................................................................... 360 a.1 serial flash loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 a.2 interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 a.2.1 uar t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 a.2.2 ssi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 a.3 packet handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 a.3.1 packet format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 a.3.2 sending packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 a.3.3 receiving packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 a.4 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 a.4.1 command_ping (0x20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 a.4.2 command_get_st a tus (0x23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 a.4.3 command_download (0x21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 a.4.4 command_send_da t a (0x24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 a.4.5 command_run (0x22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 a.4.6 command_reset (0x25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 b register quick reference ............................................................................................... 365 c ordering and contact information ................................................................................. 377 c.1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 c.2 kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 c.3 company information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 c.4 support information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 october 01, 2007 6 preliminary t able of contents
list of figures figure 1-1. stellaris ? 600 series high-level block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 2-1. cpu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 2-2. tpiu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 5-1. jt ag module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 5-2. t est access port state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 5-3. idcode register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 5-4. byp ass register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 5-5. boundary scan register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 6-1. external circuitry to extend reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 6-2. main clock t ree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 7-1. flash block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 8-1. gpio port block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 8-2. gpioda t a w rite example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 8-3. gpioda t a read example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 9-1. gptm module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 figure 9-2. 16-bit input edge count mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 figure 9-3. 16-bit input edge t ime mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 figure 9-4. 16-bit pwm mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 figure 10-1. wdt module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 figure 1 1-1. uar t module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 figure 1 1-2. uar t character frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 figure 12-1. ssi module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 figure 12-2. ti synchronous serial frame format (single t ransfer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 figure 12-3. ti synchronous serial frame format (continuous t ransfer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 figure 12-4. freescale spi format (single t ransfer) with spo=0 and sph=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 figure 12-5. freescale spi format (continuous t ransfer) with spo=0 and sph=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 figure 12-6. freescale spi frame format with spo=0 and sph=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 figure 12-7. freescale spi frame format (single t ransfer) with spo=1 and sph=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 figure 12-8. freescale spi frame format (continuous t ransfer) with spo=1 and sph=0 . . . . . . . . . . . . . . . . . . . . 260 figure 12-9. freescale spi frame format with spo=1 and sph=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 figure 12-10. microwire frame format (single frame) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 figure 12-1 1. microwire frame format (continuous t ransfer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 figure 12-12. microwire frame format, ssifss input setup and hold requirements . . . . . . . . . . . . . . . . . . . . . . . . 263 figure 13-1. i 2 c block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 figure 13-2. i 2 c bus configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 figure 13-3. st ar t and st op conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 figure 13-4. complete data t ransfer with a 7-bit address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 figure 13-5. r/s bit in first byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 figure 13-6. data v alidity during bit t ransfer on the i 2 c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 figure 13-7. master single send . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 figure 13-8. master single receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 figure 13-9. master burst send . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 figure 13-10. master burst receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 figure 13-1 1. master burst receive after burst send . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 figure 13-12. master burst send after burst receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 7 october 01, 2007 preliminary lm3s600 microcontroller
figure 13-13. slave command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 figure 14-1. analog comparator module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 figure 14-2. structure of comparator unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 figure 14-3. comparator internal reference structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 figure 15-1. pin connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 figure 18-1. load conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 figure 18-2. i 2 c t iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 figure 18-3. ssi t iming for ti frame format (frf=01), single t ransfer t iming measurement . . . . . . . . . . . . . . 352 figure 18-4. ssi t iming for microwire frame format (frf=10), single t ransfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 figure 18-5. ssi t iming for spi frame format (frf=00), with sph=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 figure 18-6. jt ag t est clock input t iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 figure 18-7. jt ag t est access port (t ap) t iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 figure 18-8. jt ag trst t iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 figure 18-9. external reset t iming ( rst ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 figure 18-10. power-on reset t iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 figure 18-1 1. brown-out reset t iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 figure 18-12. software reset t iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 figure 18-13. w atchdog reset t iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 figure 18-14. ldo reset t iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 figure 19-1. 48-pin lqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 october 01, 2007 8 preliminary t able of contents
list of t ables t able 1. documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 t able 3-1. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 t able 4-1. exception t ypes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 t able 4-2. interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 t able 5-1. jt ag port pins reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 t able 5-2. jt ag instruction register commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 t able 6-1. system control register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 t able 6-2. pll mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 t able 7-1. flash protection policy combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 t able 7-2. flash register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 t able 8-1. gpio pad configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 t able 8-2. gpio interrupt configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 t able 8-3. gpio register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 t able 9-1. 16-bit t imer with prescaler configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 t able 9-2. t imers register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 t able 10-1. w atchdog t imer register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 t able 1 1-1. uar t register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 t able 12-1. ssi register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 t able 13-1. examples of i 2 c master t imer period versus speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 t able 13-2. inter-integrated circuit (i 2 c) interface register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 t able 13-3. w rite field decoding for i2cmcs[3:0] field (sheet 1 of 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 t able 14-1. comparator 0 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 t able 14-2. comparator 1 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 t able 14-3. comparator 2 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 t able 14-4. internal reference v oltage and acrefctl field v alues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 t able 14-5. analog comparators register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 t able 16-1. signals by pin number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 t able 16-2. signals by signal name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 t able 16-3. signals by function, except for gpio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 t able 16-4. gpio pins and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 t able 17-1. t emperature characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 t able 17-2. thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 t able 18-1. maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 t able 18-2. recommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 t able 18-3. ldo regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 t able 18-4. detailed power specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 t able 18-5. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 t able 18-6. phase locked loop (pll) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 t able 18-7. clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 t able 18-8. analog comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 t able 18-9. analog comparator v oltage reference characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 t able 18-10. i 2 c characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 t able 18-1 1. ssi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 t able 18-12. jt ag characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 t able 18-13. gpio characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 t able 18-14. reset characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 9 october 01, 2007 preliminary lm3s600 microcontroller
t able c-1. part ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 october 01, 2007 10 preliminary t able of contents
list of registers system control .............................................................................................................................. 48 register 1: device identification 0 (did0), of fset 0x000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 register 2: power-on and brown-out reset control (pborctl), of fset 0x030 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 register 3: ldo power control (ldopctl), of fset 0x034 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 register 4: raw interrupt status (ris), of fset 0x050 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 register 5: interrupt mask control (imc), of fset 0x054 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 register 6: masked interrupt status and clear (misc), of fset 0x058 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 register 7: reset cause (resc), of fset 0x05c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 register 8: run-mode clock configuration (rcc), of fset 0x060 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 register 9: xt al to pll t ranslation (pllcfg), of fset 0x064 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 register 10: deep sleep clock configuration (dslpclkcfg), of fset 0x144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 register 1 1: clock v erification clear (clkvclr), of fset 0x150 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 register 12: allow unregulated ldo to reset the part (ldoarst), of fset 0x160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 register 13: device identification 1 (did1), of fset 0x004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 register 14: device capabilities 0 (dc0), of fset 0x008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 register 15: device capabilities 1 (dc1), of fset 0x010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 register 16: device capabilities 2 (dc2), of fset 0x014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 register 17: device capabilities 3 (dc3), of fset 0x018 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 register 18: device capabilities 4 (dc4), of fset 0x01c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 register 19: run mode clock gating control register 0 (rcgc0), of fset 0x100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 register 20: sleep mode clock gating control register 0 (scgc0), of fset 0x1 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 register 21: deep sleep mode clock gating control register 0 (dcgc0), of fset 0x120 . . . . . . . . . . . . . . . . . . . . . . . . . 86 register 22: run mode clock gating control register 1 (rcgc1), of fset 0x104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 register 23: sleep mode clock gating control register 1 (scgc1), of fset 0x1 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 register 24: deep sleep mode clock gating control register 1 (dcgc1), of fset 0x124 . . . . . . . . . . . . . . . . . . . . . . . . . 91 register 25: run mode clock gating control register 2 (rcgc2), of fset 0x108 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 register 26: sleep mode clock gating control register 2 (scgc2), of fset 0x1 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 register 27: deep sleep mode clock gating control register 2 (dcgc2), of fset 0x128 . . . . . . . . . . . . . . . . . . . . . . . . . 97 register 28: software reset control 0 (srcr0), of fset 0x040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 register 29: software reset control 1 (srcr1), of fset 0x044 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 register 30: software reset control 2 (srcr2), of fset 0x048 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 internal memory ........................................................................................................................... 103 register 1: flash memory address (fma), of fset 0x000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 register 2: flash memory data (fmd), of fset 0x004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 register 3: flash memory control (fmc), of fset 0x008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 register 4: flash controller raw interrupt status (fcris), of fset 0x00c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 register 5: flash controller interrupt mask (fcim), of fset 0x010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 register 6: flash controller masked interrupt status and clear (fcmisc), of fset 0x014 . . . . . . . . . . . . . . . . . . . . . 115 register 7: usec reload (usecrl), of fset 0x140 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 register 8: flash memory protection read enable (fmpre), of fset 0x130 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 register 9: flash memory protection program enable (fmppe), of fset 0x134 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 general-purpose input/outputs (gpios) ................................................................................... 119 register 1: gpio data (gpioda t a), of fset 0x000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 register 2: gpio direction (gpiodir), of fset 0x400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 register 3: gpio interrupt sense (gpiois), of fset 0x404 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 1 1 october 01, 2007 preliminary lm3s600 microcontroller
register 4: gpio interrupt both edges (gpioibe), of fset 0x408 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 register 5: gpio interrupt event (gpioiev), of fset 0x40c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 register 6: gpio interrupt mask (gpioim), of fset 0x410 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 register 7: gpio raw interrupt status (gpioris), of fset 0x414 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 register 8: gpio masked interrupt status (gpiomis), of fset 0x418 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 register 9: gpio interrupt clear (gpioicr), of fset 0x41c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 register 10: gpio alternate function select (gpioafsel), of fset 0x420 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 register 1 1: gpio 2-ma drive select (gpiodr2r), of fset 0x500 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 register 12: gpio 4-ma drive select (gpiodr4r), of fset 0x504 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 register 13: gpio 8-ma drive select (gpiodr8r), of fset 0x508 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 register 14: gpio open drain select (gpioodr), of fset 0x50c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 register 15: gpio pull-up select (gpiopur), of fset 0x510 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 register 16: gpio pull-down select (gpiopdr), of fset 0x514 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 register 17: gpio slew rate control select (gpioslr), of fset 0x518 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 register 18: gpio digital enable (gpioden), of fset 0x51c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 register 19: gpio peripheral identification 4 (gpioperiphid4), of fset 0xfd0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 register 20: gpio peripheral identification 5 (gpioperiphid5), of fset 0xfd4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 register 21: gpio peripheral identification 6 (gpioperiphid6), of fset 0xfd8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 register 22: gpio peripheral identification 7 (gpioperiphid7), of fset 0xfdc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 register 23: gpio peripheral identification 0 (gpioperiphid0), of fset 0xfe0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 register 24: gpio peripheral identification 1 (gpioperiphid1), of fset 0xfe4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 register 25: gpio peripheral identification 2 (gpioperiphid2), of fset 0xfe8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 register 26: gpio peripheral identification 3 (gpioperiphid3), of fset 0xfec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 register 27: gpio primecell identification 0 (gpiopcellid0), of fset 0xff0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 register 28: gpio primecell identification 1 (gpiopcellid1), of fset 0xff4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 register 29: gpio primecell identification 2 (gpiopcellid2), of fset 0xff8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 register 30: gpio primecell identification 3 (gpiopcellid3), of fset 0xffc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 general-purpose t imers ............................................................................................................. 157 register 1: gptm configuration (gptmcfg), of fset 0x000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 register 2: gptm t imera mode (gptmt amr), of fset 0x004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 register 3: gptm t imerb mode (gptmtbmr), of fset 0x008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 register 4: gptm control (gptmctl), of fset 0x00c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 register 5: gptm interrupt mask (gptmimr), of fset 0x018 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 register 6: gptm raw interrupt status (gptmris), of fset 0x01c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 register 7: gptm masked interrupt status (gptmmis), of fset 0x020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 register 8: gptm interrupt clear (gptmicr), of fset 0x024 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 register 9: gptm t imera interval load (gptmt ailr), of fset 0x028 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 register 10: gptm t imerb interval load (gptmtbilr), of fset 0x02c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 register 1 1: gptm t imera match (gptmt ama tchr), of fset 0x030 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 register 12: gptm t imerb match (gptmtbma tchr), of fset 0x034 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 register 13: gptm t imera prescale (gptmt apr), of fset 0x038 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 register 14: gptm t imerb prescale (gptmtbpr), of fset 0x03c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 register 15: gptm t imera prescale match (gptmt apmr), of fset 0x040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 register 16: gptm t imerb prescale match (gptmtbpmr), of fset 0x044 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 register 17: gptm t imera (gptmt ar), of fset 0x048 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 register 18: gptm t imerb (gptmtbr), of fset 0x04c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 w atchdog t imer ........................................................................................................................... 193 register 1: w atchdog load (wdtload), of fset 0x000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 october 01, 2007 12 preliminary t able of contents
register 2: w atchdog v alue (wdtv alue), of fset 0x004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 register 3: w atchdog control (wdtctl), of fset 0x008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 register 4: w atchdog interrupt clear (wdticr), of fset 0x00c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 register 5: w atchdog raw interrupt status (wdtris), of fset 0x010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 register 6: w atchdog masked interrupt status (wdtmis), of fset 0x014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 register 7: w atchdog t est (wdttest), of fset 0x418 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 register 8: w atchdog lock (wdtlock), of fset 0xc00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 register 9: w atchdog peripheral identification 4 (wdtperiphid4), of fset 0xfd0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 register 10: w atchdog peripheral identification 5 (wdtperiphid5), of fset 0xfd4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 register 1 1: w atchdog peripheral identification 6 (wdtperiphid6), of fset 0xfd8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 register 12: w atchdog peripheral identification 7 (wdtperiphid7), of fset 0xfdc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 register 13: w atchdog peripheral identification 0 (wdtperiphid0), of fset 0xfe0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 register 14: w atchdog peripheral identification 1 (wdtperiphid1), of fset 0xfe4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 register 15: w atchdog peripheral identification 2 (wdtperiphid2), of fset 0xfe8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 register 16: w atchdog peripheral identification 3 (wdtperiphid3), of fset 0xfec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 register 17: w atchdog primecell identification 0 (wdtpcellid0), of fset 0xff0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 register 18: w atchdog primecell identification 1 (wdtpcellid1), of fset 0xff4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 register 19: w atchdog primecell identification 2 (wdtpcellid2), of fset 0xff8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 register 20: w atchdog primecell identification 3 (wdtpcellid3 ), of fset 0xffc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 universal asynchronous receivers/t ransmitters (uart s) ..................................................... 216 register 1: uar t data (uar tdr), of fset 0x000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 register 2: uar t receive status/error clear (uar trsr/uar tecr), of fset 0x004 . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 register 3: uar t flag (uar tfr), of fset 0x018 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 register 4: uar t integer baud-rate divisor (uar tibrd), of fset 0x024 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 register 5: uar t fractional baud-rate divisor (uar tfbrd), of fset 0x028 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 register 6: uar t line control (uar tlcrh), of fset 0x02c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 register 7: uar t control (uar tctl), of fset 0x030 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 register 8: uar t interrupt fifo level select (uar tifls), of fset 0x034 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 register 9: uar t interrupt mask (uar tim), of fset 0x038 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 register 10: uar t raw interrupt status (uar tris), of fset 0x03c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 register 1 1: uar t masked interrupt status (uar tmis), of fset 0x040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 register 12: uar t interrupt clear (uar ticr), of fset 0x044 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 register 13: uar t peripheral identification 4 (uar tperiphid4), of fset 0xfd0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 register 14: uar t peripheral identification 5 (uar tperiphid5), of fset 0xfd4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 register 15: uar t peripheral identification 6 (uar tperiphid6), of fset 0xfd8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 register 16: uar t peripheral identification 7 (uar tperiphid7), of fset 0xfdc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 register 17: uar t peripheral identification 0 (uar tperiphid0), of fset 0xfe0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 register 18: uar t peripheral identification 1 (uar tperiphid1), of fset 0xfe4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 register 19: uar t peripheral identification 2 (uar tperiphid2), of fset 0xfe8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 register 20: uar t peripheral identification 3 (uar tperiphid3), of fset 0xfec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 register 21: uar t primecell identification 0 (uar tpcellid0), of fset 0xff0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 register 22: uar t primecell identification 1 (uar tpcellid1), of fset 0xff4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 register 23: uar t primecell identification 2 (uar tpcellid2), of fset 0xff8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 register 24: uar t primecell identification 3 (uar tpcellid3), of fset 0xffc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 synchronous serial interface (ssi) ............................................................................................ 254 register 1: ssi control 0 (ssicr0), of fset 0x000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 register 2: ssi control 1 (ssicr1), of fset 0x004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 register 3: ssi data (ssidr), of fset 0x008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 13 october 01, 2007 preliminary lm3s600 microcontroller
register 4: ssi status (ssisr), of fset 0x00c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 register 5: ssi clock prescale (ssicpsr), of fset 0x010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 register 6: ssi interrupt mask (ssiim), of fset 0x014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 register 7: ssi raw interrupt status (ssiris), of fset 0x018 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 register 8: ssi masked interrupt status (ssimis), of fset 0x01c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 register 9: ssi interrupt clear (ssiicr), of fset 0x020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 register 10: ssi peripheral identification 4 (ssiperiphid4), of fset 0xfd0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 register 1 1: ssi peripheral identification 5 (ssiperiphid5), of fset 0xfd4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 register 12: ssi peripheral identification 6 (ssiperiphid6), of fset 0xfd8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 register 13: ssi peripheral identification 7 (ssiperiphid7), of fset 0xfdc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 register 14: ssi peripheral identification 0 (ssiperiphid0), of fset 0xfe0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 register 15: ssi peripheral identification 1 (ssiperiphid1), of fset 0xfe4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 register 16: ssi peripheral identification 2 (ssiperiphid2), of fset 0xfe8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 register 17: ssi peripheral identification 3 (ssiperiphid3), of fset 0xfec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 register 18: ssi primecell identification 0 (ssipcellid0), of fset 0xff0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 register 19: ssi primecell identification 1 (ssipcellid1), of fset 0xff4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 register 20: ssi primecell identification 2 (ssipcellid2), of fset 0xff8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 register 21: ssi primecell identification 3 (ssipcellid3), of fset 0xffc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 inter-integrated circuit (i 2 c) interface ........................................................................................ 291 register 1: i 2 c master slave address (i2cmsa), of fset 0x000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 register 2: i 2 c master control/status (i2cmcs), of fset 0x004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 register 3: i 2 c master data (i2cmdr), of fset 0x008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 register 4: i 2 c master t imer period (i2cmtpr), of fset 0x00c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 register 5: i 2 c master interrupt mask (i2cmimr), of fset 0x010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 register 6: i 2 c master raw interrupt status (i2cmris), of fset 0x014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 register 7: i 2 c master masked interrupt status (i2cmmis), of fset 0x018 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 register 8: i 2 c master interrupt clear (i2cmicr), of fset 0x01c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 register 9: i 2 c master configuration (i2cmcr), of fset 0x020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 register 10: i 2 c slave own address (i2csoar), of fset 0x000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 register 1 1: i 2 c slave control/status (i2cscsr), of fset 0x004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 register 12: i 2 c slave data (i2csdr), of fset 0x008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 register 13: i 2 c slave interrupt mask (i2csimr), of fset 0x00c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 register 14: i 2 c slave raw interrupt status (i2csris), of fset 0x010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 register 15: i 2 c slave masked interrupt status (i2csmis), of fset 0x014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 register 16: i 2 c slave interrupt clear (i2csicr), of fset 0x018 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 analog comparators ................................................................................................................... 326 register 1: analog comparator masked interrupt status (acmis), of fset 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 register 2: analog comparator raw interrupt status (acris), of fset 0x04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 register 3: analog comparator interrupt enable (acinten), of fset 0x08 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 register 4: analog comparator reference v oltage control (acrefctl), of fset 0x10 . . . . . . . . . . . . . . . . . . . . . . . . . 335 register 5: analog comparator status 0 (acst a t0), of fset 0x20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 register 6: analog comparator status 1 (acst a t1), of fset 0x40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 register 7: analog comparator status 2 (acst a t2), of fset 0x60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 register 8: analog comparator control 0 (acctl0), of fset 0x24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 register 9: analog comparator control 1 (acctl1), of fset 0x44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 register 10: analog comparator control 2 (acctl2), of fset 0x64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 october 01, 2007 14 preliminary t able of contents
about this document this data sheet provides reference information for the lm3s600 microcontroller , describing the functional blocks of the system-on-chip (soc) device designed around the arm? cortex?-m3 core. audience this manual is intended for system software developers, hardware designers, and application developers. about this manual this document is organized into sections that correspond to each major feature. related documents the following documents are referenced by the data sheet, and available on the documentation cd or from the luminary micro web site at www .luminarymicro.com: arm? cortex?-m3 t echnical reference manual arm? coresight t echnical reference manual arm? v7-m architecture application level reference manual the following related documents are also referenced: ieee standard 1 149.1-t est access port and boundary-scan architecture this documentation list was current as of publication date. please check the luminary micro web site for additional documentation, including application notes and white papers. documentation conventions this document uses the conventions shown in t able 1 on page 15 . t able 1. documentation conventions meaning notation general register notation apb registers are indicated in uppercase bold. for example, pborctl is the power-on and brown-out reset control register . if a register name contains a lowercase n, it represents more than one register . for example, srcrn represents any (or all) of the three software reset control registers: srcr0, srcr1 , and srcr2 . register a single bit in a register . bit t wo or more consecutive and related bits. bit field a hexadecimal increment to a register's address, relative to that module's base address as specified in memory map on page 34 . of fset 0x nnn registers are numbered consecutively throughout the document to aid in referencing them. the register number has no meaning to software. register n 15 october 01, 2007 preliminary lm3s600 microcontroller
meaning notation register bits marked reserved are reserved for future use. in most cases, reserved bits are set to 0; however , user software should not rely on the value of a reserved bit. t o provide software compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. reserved the range of register bits inclusive from xx to yy . for example, 31:15 means bits 15 through 31 in that register . yy:xx this value in the register bit diagram indicates whether software running on the controller can change the value of the bit field. register bit/field t ypes software can read this field. the bit or field is cleared by hardware after reading the bit/field. rc software can read this field. always write the chip reset value. ro software can read or write this field. r/w software can read or write this field. a write of a 0 to a w1c bit does not af fect the bit value in the register . a write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. this register type is primarily used for clearing interrupt status bits where the read operation provides the interrupt status and the write of the read value clears only the interrupts being reported at the time the register was read. r/w1c software can write this field. a write of a 0 to a w1c bit does not af fect the bit value in the register . a write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. a read of the register returns no meaningful data. this register is typically used to clear the corresponding bit in an interrupt register . w1c only a write by software is valid; a read of the register returns no meaningful data. wo this value in the register bit diagram shows the bit/field value after any reset, unless noted. register bit/field reset v alue bit cleared to 0 on chip reset. 0 bit set to 1 on chip reset. 1 nondeterministic. - pin/signal notation pin alternate function; a pin defaults to the signal without the brackets. [ ] refers to the physical connection on the package. pin refers to the electrical signal encoding of a pin. signal change the value of the signal from the logically false state to the logically t rue state. for active high signals, the asserted signal value is 1 (high); for active low signals, the asserted signal value is 0 (low). the active polarity (high or low) is defined by the signal name (see signal and signal below). assert a signal change the value of the signal from the logically t rue state to the logically false state. deassert a signal signal names are in uppercase and in the courier font. an overbar on a signal name indicates that it is active low . t o assert signal is to drive it low; to deassert signal is to drive it high. signal signal names are in uppercase and in the courier font. an active high signal has no overbar . t o assert signal is to drive it high; to deassert signal is to drive it low . signal numbers an uppercase x indicates any of several values is allowed, where x can be any legal pattern. for example, a binary value of 0x00 can be either 0100 or 0000, a hex value of 0xx is 0x0 or 0x1, and so on. x hexadecimal numbers have a prefix of 0x. for example, 0x00ff is the hexadecimal number ff . all other numbers within register tables are assumed to be binary . within conceptual information, binary numbers are indicated with a b suf fix, for example, 101 1b, and decimal numbers are written without a prefix or suf fix. 0x october 01, 2007 16 preliminary about this document
1 architectural overview the luminary micro stellaris ? family of microcontrollersthe first arm? cortex?-m3 based controllersbrings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. these pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint. the lm3s600 microcontroller is targeted for industrial applications, including test and measurement equipment, factory automation, hv ac and building control, motion control, medical instrumentation, fire and security , and power/energy . in addition, the lm3s600 microcontroller of fers the advantages of arm's widely available development tools, system-on-chip (soc) infrastructure ip applications, and a large user community . additionally , the microcontroller uses arm's thumb?-compatible thumb-2 instruction set to reduce memory requirements and, thereby , cost. finally , the lm3s600 microcontroller is code-compatible to all members of the extensive stellaris ? family; providing flexibility to fit our customers' precise needs. luminary micro of fers a complete solution to get to market quickly , with evaluation and development boards, white papers and application notes, an easy-to-use peripheral driver library , and a strong support, sales, and distributor network. 1.1 product features the lm3s600 microcontroller includes the following product features: 32-bit risc performance C 32-bit arm? cortex?-m3 v7m architecture optimized for small-footprint embedded applications C system timer (syst ick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism C thumb?-compatible thumb-2-only instruction set processor core for high code density C 50-mhz operation C hardware-division and single-cycle-multiplication C integrated nested v ectored interrupt controller (nvic) providing deterministic interrupt handling C 21 interrupts with eight priority levels C memory protection unit (mpu), providing a privileged mode for protected operating system functionality C unaligned data access, enabling data to be ef ficiently packed into memory C atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control internal memory 17 october 01, 2007 preliminary lm3s600 microcontroller
32 kb single-cycle flash C ? user-managed flash block protection on a 2-kb block basis ? user-managed flash data programming ? user-defined and managed flash-protection block C 8 kb single-cycle sram general-purpose t imers C three general-purpose t imer modules (gptm), each of which provides two 16-bit timer/counters. each gptm can be configured to operate independently as timers or event counters as a single 32-bit timer , as one 32-bit real-t ime clock (r tc) to event capture, or for pulse width modulation (pwm) C 32-bit t imer modes ? programmable one-shot timer ? programmable periodic timer ? real-t ime clock when using an external 32.768-khz clock as the input ? user-enabled stalling in periodic and one-shot mode when the controller asserts the cpu halt flag during debug C 16-bit t imer modes ? general-purpose timer function with an 8-bit prescaler ? programmable one-shot timer ? programmable periodic timer ? user-enabled stalling when the controller asserts cpu halt flag during debug C 16-bit input capture modes ? input edge count capture ? input edge time capture C 16-bit pwm mode ? simple pwm mode with software-programmable output inversion of the pwm signal arm firm-compliant w atchdog t imer C 32-bit down counter with a programmable load register C separate watchdog clock with an enable C programmable interrupt generation logic with interrupt masking C lock register protection from runaway software october 01, 2007 18 preliminary architectural overview
C reset generation logic with an enable/disable C user-enabled stalling when the controller asserts the cpu halt flag during debug synchronous serial interface (ssi) C master or slave operation C programmable clock bit rate and prescale C separate transmit and receive fifos, 16 bits wide, 8 locations deep C programmable interface operation for freescale spi, microwire, or t exas instruments synchronous serial interfaces C programmable data frame size from 4 to 16 bits C internal loopback test mode for diagnostic/debug testing uar t C t wo fully programmable 16c550-type uar t s C separate 16x8 transmit (tx) and 16x12 receive (rx) fifos to reduce cpu interrupt service loading C programmable baud-rate generator with fractional divider C programmable fifo length, including 1-byte deep operation providing conventional double-buf fered interface C fifo trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 C standard asynchronous communication bits for start, stop, and parity C false-start-bit detection C line-break generation and detection analog comparators C three independent integrated analog comparators C configurable for output to: drive an output pin or generate an interrupt C compare external pin input to external pin input or to internal programmable voltage reference i 2 c C master and slave receive and transmit operation with transmission speed up to 100 kbps in standard mode and 400 kbps in fast mode C interrupt generation C master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode 19 october 01, 2007 preliminary lm3s600 microcontroller
gpios C 8-36 gpios, depending on configuration C 5-v-tolerant input/outputs C programmable interrupt generation as either edge-triggered or level-sensitive C bit masking in both read and write operations through address lines C programmable control for gpio pad configuration: ? w eak pull-up or pull-down resistors ? 2-ma, 4-ma, and 8-ma pad drive ? slew rate control for the 8-ma drive ? open drain enables ? digital input enables power C on-chip low drop-out (ldo) voltage regulator , with programmable output user-adjustable from 2.25 v to 2.75 v C low-power options on controller: sleep and deep-sleep modes C low-power options for peripherals: software controls shutdown of individual peripherals C user-enabled ldo unregulated voltage detection and automatic reset C 3.3-v supply brown-out detection and reporting via interrupt or reset flexible reset sources C power-on reset (por) C reset pin assertion C brown-out (bor) detector alerts to system power drops C software reset C w atchdog timer reset C internal low drop-out (ldo) regulator output goes unregulated additional features C six reset sources C programmable clock source control C clock gating to individual peripherals for power savings october 01, 2007 20 preliminary architectural overview
C ieee 1 149.1-1990 compliant t est access port (t ap) controller C debug access via jt ag and serial wire interfaces C full jt ag boundary scan industrial-range 48-pin rohs-compliant lqfp package 1.2 t arget applications factory automation and control industrial control power devices building and home automation stepper motors brushless dc motors ac induction motors 1.3 high-level block diagram figure 1-1 on page 22 represents the full set of features in the stellaris ? 600 series of devices; not all features may be available on the lm3s600 microcontroller . 21 october 01, 2007 preliminary lm3s600 microcontroller
figure 1-1. stellaris ? 600 series high-level block diagram 1.4 functional overview the following sections provide an overview of the features of the lm3s600 microcontroller . the page number in parenthesis indicates where that feature is discussed in detail. ordering and support information can be found in ordering and contact information on page 377 . october 01, 2007 22 preliminary architectural overview
1.4.1 arm cortex?-m3 1.4.1.1 processor core (see page 28 ) all members of the stellaris ? product family , including the lm3s600 microcontroller , are designed around an arm cortex?-m3 processor core. the arm cortex-m3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low-power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. arm cortex-m3 processor core on page 28 provides an overview of the arm core; the core is detailed in the arm? cortex?-m3 t echnical reference manual . 1.4.1.2 system t imer (syst ick) cortex-m3 includes an integrated system timer , syst ick. syst ick provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. the counter can be used in several dif ferent ways, for example: an r t os tick timer which fires at a programmable rate (for example, 100 hz) and invokes a syst ick routine. a high-speed alarm timer using the system clock. a variable rate alarm or signal timerthe duration is range-dependent on the reference clock used and the dynamic range of the counter . a simple counter . software can use this to measure time to completion and time used. an internal clock source control based on missing/meeting durations. the countflag bit-field in the control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. 1.4.1.3 nested v ectored interrupt controller (nvic) the lm3s600 controller includes the arm nested v ectored interrupt controller (nvic) on the arm cortex-m3 core. the nvic and cortex-m3 prioritize and handle all exceptions. all exceptions are handled in handler mode. the processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the interrupt service routine (isr). the vector is fetched in parallel to the state saving, which enables ef ficient interrupt entry . the processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. software can set eight priority levels on 7 exceptions (system handlers) and 21 interrupts. interrupts on page 36 provides an overview of the nvic controller and the interrupt map. exceptions and interrupts are detailed in the arm? cortex?-m3 t echnical reference manual . 1.4.2 motor control peripherals t o enhance motor control, the lm3s600 controller features pulse width modulation (pwm) outputs. 1.4.2.1 pwm (see page 163 ) pulse width modulation (pwm) is a powerful technique for digitally encoding analog signal levels. high-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. t ypical applications include switching power supplies and motor control. 23 october 01, 2007 preliminary lm3s600 microcontroller
on the lm3s600, pwm motion control functionality can be achieved through the motion control features of the general-purpose timers (using the ccp pins). ccp pins (see page 163 ) the general-purpose t imer module's ccp (capture compare pwm) pins are software programmable to support a simple pwm mode with a software-programmable output inversion of the pwm signal. 1.4.3 analog peripherals for support of analog signals, the lm3s600 microcontroller of fers three analog comparators. 1.4.3.1 analog comparators (see page 326 ) an analog comparator is a peripheral that compares two analog voltages, and provides a logical output that signals the comparison result. the lm3s600 microcontroller provides three independent integrated analog comparators that can be configured to drive an output or generate an interrupt . a comparator can compare a test voltage against any one of these voltages: an individual external reference voltage a shared single external reference voltage a shared internal reference voltage the comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts to cause it to start capturing a sample sequence. 1.4.4 serial communications peripherals the lm3s600 controller supports both asynchronous and synchronous serial communications with: t wo fully programmable 16c550-type uar t s one ssi module one i 2 c module 1.4.4.1 uart (see page 216 ) a universal asynchronous receiver/t ransmitter (uar t) is an integrated circuit used for rs-232c serial communications, containing a transmitter (parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately . the lm3s600 controller includes two fully programmable 16c550-type uar t s that support data transfer speeds up to 460.8 kbps. (although similar in functionality to a 16c550 uar t , it is not register-compatible.) separate 16x8 transmit (tx) and 16x12 receive (rx) fifos reduce cpu interrupt service loading. the uar t can generate individually masked interrupts from the rx, tx, modem status, and error conditions. the module provides a single combined interrupt when any of the interrupts are asserted and are unmasked. october 01, 2007 24 preliminary architectural overview
1.4.4.2 ssi (see page 254 ) synchronous serial interface (ssi) is a four-wire bi-directional communications interface. the lm3s600 controller includes one ssi module that provides the functionality for synchronous serial communications with peripheral devices, and can be configured to use the freescale spi, microwire, or ti synchronous serial interface frame formats. the size of the data frame is also configurable, and can be set between 4 and 16 bits, inclusive. the ssi module performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral device. the tx and rx paths are buf fered with internal fifos, allowing up to eight 16-bit values to be stored independently . the ssi module can be configured as either a master or slave device. as a slave device, the ssi module can also be configured to disable its output, which allows a master device to be coupled with multiple slave devices. the ssi module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the ssi module's input clock. bit rates are generated based on the input clock and the maximum bit rate is determined by the connected peripheral. 1.4.4.3 i 2 c (see page 291 ) the inter-integrated circuit (i 2 c) bus provides bi-directional data transfer through a two-wire design (a serial data line sda and a serial clock line scl). the i 2 c bus interfaces to external i 2 c devices such as serial memory (rams and roms), networking devices, lcds, tone generators, and so on. the i 2 c bus may also be used for system testing and diagnostic purposes in product development and manufacture. the lm3s600 controller includes one i 2 c module that provides the ability to communicate to other ic devices over an i 2 c bus. the i 2 c bus supports devices that can both transmit and receive (write and read) data. devices on the i 2 c bus can be designated as either a master or a slave. the i 2 c module supports both sending and receiving data as either a master or a slave, and also supports the simultaneous operation as both a master and a slave. the four i 2 c modes are: master t ransmit, master receive, slave t ransmit, and slave receive. a stellaris ? i 2 c module can operate at two speeds: standard (100 kbps) and fast (400 kbps). both the i 2 c master and slave can generate interrupts. the i 2 c master generates interrupts when a transmit or receive operation completes (or aborts due to an error). the i 2 c slave generates interrupts when data has been sent or requested by a master . 1.4.5 system peripherals 1.4.5.1 programmable gpios (see page 119 ) general-purpose input/output (gpio) pins of fer flexibility for a variety of connections. the stellaris ? gpio module is composed of five physical gpio blocks, each corresponding to an individual gpio port. the gpio module is firm-compliant (compliant to the arm foundation ip for real-t ime microcontrollers specification) and supports 8-36 programmable input/output pins. the number of gpios available depends on the peripherals being used (see signal t ables on page 340 for the signals available to each gpio pin). 25 october 01, 2007 preliminary lm3s600 microcontroller
the gpio module features programmable interrupt generation as either edge-triggered or level-sensitive on all pins, programmable control for gpio pad configuration, and bit masking in both read and write operations through address lines. 1.4.5.2 three programmable t imers (see page 157 ) programmable timers can be used to count or time external events that drive the t imer input pins. the stellaris ? general-purpose t imer module (gptm) contains three gptm blocks. each gptm block provides two 16-bit timer/counters that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit real-t ime clock (r tc). when configured in 32-bit mode, a timer can run as a one-shot timer , periodic timer , or real-t ime clock (r tc). when in 16-bit mode, a timer can run as a one-shot timer or periodic timer , and can extend its precision by using an 8-bit prescaler . a 16-bit timer can also be configured for event capture or pulse width modulation (pwm) generation. 1.4.5.3 w atchdog t imer (see page 193 ) a watchdog timer can generate nonmaskable interrupts (nmis) or a reset when a time-out value is reached. the watchdog timer is used to regain control when a system has failed due to a software error or to the failure of an external device to respond in the expected way . the stellaris ? w atchdog t imer module consists of a 32-bit down counter , a programmable load register , interrupt generation logic, and a locking register . the w atchdog t imer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. once the w atchdog t imer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. 1.4.6 memory peripherals the lm3s600 controller of fers both single-cycle sram and single-cycle flash memory . 1.4.6.1 sram (see page 103 ) the lm3s600 static random access memory (sram) controller supports 8 kb sram. the internal sram of the stellaris ? devices is located at of fset 0x0000.0000 of the device memory map. t o reduce the number of time-consuming read-modify-write (rmw) operations, arm has introduced bit-banding technology in the new cortex-m3 processor . with a bit-band-enabled processor , certain regions in the memory map (sram and peripheral space) can use address aliases to access individual bits in a single, atomic operation. 1.4.6.2 flash (see page 104 ) the lm3s600 flash controller supports 32 kb of flash memory . the flash is organized as a set of 1-kb blocks that can be individually erased. erasing a block causes the entire contents of the block to be reset to all 1s. these blocks are paired into a set of 2-kb blocks that can be individually protected. the blocks can be marked as read-only or execute-only , providing dif ferent levels of code protection. read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger . october 01, 2007 26 preliminary architectural overview
1.4.7 additional features 1.4.7.1 memory map (see page 34 ) a memory map lists the location of instructions and data in memory . the memory map for the lm3s600 controller can be found in memory map on page 34 . register addresses are given as a hexadecimal increment, relative to the module's base address as shown in the memory map. the arm? cortex?-m3 t echnical reference manual provides further information on the memory map. 1.4.7.2 jt ag t ap controller (see page 38 ) the joint t est action group (jt ag) port provides a standardized serial interface for controlling the t est access port (t ap) and associated test logic. the t ap , jt ag instruction register , and jt ag data registers can be used to test the interconnects of assembled printed circuit boards, obtain manufacturing information on the components, and observe and/or control the inputs and outputs of the controller during normal operation. the jt ag port provides a high degree of testability and chip-level access at a low cost. the jt ag port is comprised of the standard five pins: trst , tck , tms , tdi , and tdo . data is transmitted serially into the controller on tdi and out of the controller on tdo . the interpretation of this data is dependent on the current state of the t ap controller . for detailed information on the operation of the jt ag port and t ap controller , please refer to the ieee standard 1 149.1-t est access port and boundary-scan architecture . the luminary micro jt ag controller works with the arm jt ag controller built into the cortex-m3 core. this is implemented by multiplexing the tdo outputs from both jt ag controllers. arm jt ag instructions select the arm tdo output while luminary micro jt ag instructions select the luminary micro tdo outputs. the multiplexer is controlled by the luminary micro jt ag controller , which has comprehensive programming for the arm, luminary micro, and unimplemented jt ag instructions. 1.4.7.3 system control and clocks (see page 48 ) system control determines the overall operation of the device. it provides information about the device, controls the clocking of the device and individual peripherals, and handles reset detection and reporting. 1.4.8 hardware details details on the pins and package can be found in the following sections: pin diagram on page 339 signal t ables on page 340 operating characteristics on page 347 electrical characteristics on page 348 package information on page 358 27 october 01, 2007 preliminary lm3s600 microcontroller
2 arm cortex-m3 processor core the arm cortex-m3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. features include: compact core. thumb-2 instruction set, delivering the high-performance expected of an arm core in the memory size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of memory for microcontroller class applications. rapid application execution through harvard architecture characterized by separate buses for instruction and data. exceptional interrupt handling, by implementing the register manipulations required for handling an interrupt in hardware. memory protection unit (mpu) to provide a privileged mode of operation for complex applications. migration from the arm7? processor family for better performance and power ef ficiency . full-featured debug solution with a: C serial wire jt ag debug port (swj-dp) C flash patch and breakpoint (fpb) unit for implementing breakpoints C data w atchpoint and t rigger (dwt) unit for implementing watchpoints, trigger resources, and system profiling C instrumentation t race macrocell (itm) for support of printf style debugging C t race port interface unit (tpiu) for bridging to a t race port analyzer the stellaris ? family of microcontrollers builds on this core to bring high-performance 32-bit computing to cost-sensitive embedded microcontroller applications, such as factory automation and control, industrial control power devices, building and home automation, and stepper motors. for more information on the arm cortex-m3 processor core, see the arm? cortex?-m3 t echnical reference manual . for information on swj-dp , see the arm? coresight t echnical reference manual . october 01, 2007 28 preliminary arm cortex-m3 processor core
2.1 block diagram figure 2-1. cpu block diagram 2.2 functional description important: the arm? cortex?-m3 t echnical reference manual describes all the features of an arm cortex-m3 in detail. however , these features dif fer based on the implementation. this section describes the stellaris ? implementation. luminary micro has implemented the arm cortex-m3 core as shown in figure 2-1 on page 29 . as noted in the arm? cortex?-m3 t echnical reference manual , several cortex-m3 components are flexible in their implementation: sw/jt ag-dp , etm, tpiu, the rom table, the mpu, and the nested v ectored interrupt controller (nvic). each of these is addressed in the sections that follow . 2.2.1 serial w ire and jt ag debug luminary micro has replaced the arm sw-dp and jt ag-dp with the arm coresight?-compliant serial wire jt ag debug port (swj-dp) interface. this means chapter 12, debug port, of the arm? cortex?-m3 t echnical reference manual does not apply to stellaris ? devices. the swj-dp interface combines the swd and jt ag debug ports into one module. see the coresight? design kit t echnical reference manual for details on swj-dp . 29 october 01, 2007 preliminary lm3s600 microcontroller private peripheral bus ( internal) data w atchpoint and t race interrupts debug sleep instrumentation t race macrocell t race port interface unit cm3 core instructions data flash patch and breakpoint memory protection unit adv . high- perf . bus access port nested v ectored interrupt controller serial wire jt ag debug port bus matrix adv . peripheral bus i-code bus d-code bus system bus rom t able private peripheral bus ( external) serial wire output t race port ( swo) arm cortex -m3
2.2.2 embedded t race macrocell (etm) etm was not implemented in the stellaris ? devices. this means chapters 15 and 16 of the arm? cortex?-m3 t echnical reference manual can be ignored. 2.2.3 t race port interface unit (tpiu) the tpiu acts as a bridge between the cortex-m3 trace data from the itm, and an of f-chip t race port analyzer . the stellaris ? devices have implemented tpiu as shown in figure 2-2 on page 30 . this is similar to the non-etm version described in the arm? cortex?-m3 t echnical reference manual , however , swj-dp only provides swv output for the tpiu. figure 2-2. tpiu block diagram 2.2.4 rom t able the default rom table was implemented as described in the arm? cortex?-m3 t echnical reference manual . 2.2.5 memory protection unit (mpu) the memory protection unit (mpu) is included on the lm3s600 controller and supports the standard armv7 protected memory system architecture (pmsa) model. the mpu provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system. 2.2.6 nested v ectored interrupt controller (nvic) the nested v ectored interrupt controller (nvic): facilitates low-latency exception and interrupt handling controls power management implements system control registers october 01, 2007 30 preliminary arm cortex-m3 processor core a tb interface asynchronous fifo apb interface t race out ( serializer) debug a tb slave port apb slave port serial wire t race port ( swo)
the nvic supports up to 240 dynamically reprioritizable interrupts each with up to 256 levels of priority . the nvic and the processor core interface are closely coupled, which enables low latency interrupt processing and ef ficient processing of late arriving interrupts. the nvic maintains knowledge of the stacked (nested) interrupts to enable tail-chaining of interrupts. y ou can only fully access the nvic from privileged mode, but you can pend interrupts in user-mode if you enable the configuration control register (see the arm? cortex?-m3 t echnical reference manual). any other user-mode access causes a bus fault. all nvic registers are accessible using byte, halfword, and word unless otherwise stated. all nvic registers and system debug registers are little endian regardless of the endianness state of the processor . 2.2.6.1 interrupts the arm? cortex?-m3 t echnical reference manual describes the maximum number of interrupts and interrupt priorities. the lm3s600 microcontroller supports 21 interrupts with eight priority levels. 2.2.6.2 system t imer (syst ick) cortex-m3 includes an integrated system timer , syst ick. syst ick provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. the counter can be used in several dif ferent ways, for example: an r t os tick timer which fires at a programmable rate (for example, 100 hz) and invokes a syst ick routine. a high-speed alarm timer using the system clock. a variable rate alarm or signal timerthe duration is range-dependent on the reference clock used and the dynamic range of the counter . a simple counter . software can use this to measure time to completion and time used. an internal clock source control based on missing/meeting durations. the countflag bit-field in the control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. functional description the timer consists of three registers: a control and status counter to configure its clock, enable the counter , enable the syst ick interrupt, and determine counter status. the reload value for the counter , used to provide the counter's wrap value. the current value of the counter . a fourth register , the syst ick calibration v alue register , is not implemented in the stellaris ? devices. when enabled, the timer counts down from the reload value to zero, reloads (wraps) to the value in the syst ick reload v alue register on the next clock edge, then decrements on subsequent clocks. w riting a value of zero to the reload v alue register disables the counter on the next wrap. when the counter reaches zero, the countflag status bit is set. the countflag bit clears on reads. 31 october 01, 2007 preliminary lm3s600 microcontroller
w riting to the current v alue register clears the register and the countflag status bit. the write does not trigger the syst ick exception logic. on a read, the current value is the value of the register at the time the register is accessed. if the core is in debug state (halted), the counter will not decrement. the timer is clocked with respect to a reference clock. the reference clock can be the core clock or an external clock source. syst ick control and status register use the syst ick control and status register to enable the syst ick features. the reset is 0x0000.0000. description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:17 returns 1 if timer counted to 0 since last time this was read. clears on read by application. if read by the debugger using the dap , this bit is cleared on read-only if the mastert ype bit in the ahb-ap control register is set to 0. otherwise, the countflag bit is not changed by the debugger read. 0 r/w countflag 16 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:3 0 = external reference clock. (not implemented for stellaris microcontrollers.) 1 = core clock. if no reference clock is provided, it is held at 1 and so gives the same time as the core clock. the core clock must be at least 2.5 times faster than the reference clock. if it is not, the count values are unpredictable. 0 r/w clksource 2 1 = counting down to 0 pends the syst ick handler . 0 = counting down to 0 does not pend the syst ick handler . software can use the countflag to determine if ever counted to 0. 0 r/w tickint 1 1 = counter operates in a multi-shot way . that is, counter loads with the reload value and then begins counting down. on reaching 0, it sets the countflag to 1 and optionally pends the syst ick handler , based on tickint . it then loads the reload value again, and begins counting. 0 = counter disabled. 0 r/w enable 0 syst ick reload v alue register use the syst ick reload v alue register to specify the start value to load into the current value register when the counter reaches 0. it can be any value between 1 and 0x00ff .ffff . a start value of 0 is possible, but has no ef fect because the syst ick interrupt and countflag are activated when counting from 1 to 0. therefore, as a multi-shot timer , repeated over and over , it fires every n+1 clock pulse, where n is any value from 1 to 0x00ff .ffff . so, if the tick interrupt is required every 100 clock pulses, 99 must be written into the reload. if a new value is written on each tick interrupt, so treated as single shot, then the actual count down must be written. for example, if a tick is next required after 400 clock pulses, 400 must be written into the reload. description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:24 october 01, 2007 32 preliminary arm cortex-m3 processor core
description reset t ype name bit/field v alue to load into the syst ick current v alue register when the counter reaches 0. - w1c reload 23:0 syst ick current v alue register use the syst ick current v alue register to find the current value in the register . description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:24 current value at the time the register is accessed. no read-modify-write protection is provided, so change with care. this register is write-clear . w riting to it with any value clears the register to 0. clearing this register also clears the countflag bit of the syst ick control and status register . - w1c current 23:0 syst ick calibration v alue register the syst ick calibration v alue register is not implemented. 33 october 01, 2007 preliminary lm3s600 microcontroller
3 memory map the memory map for the lm3s600 controller is provided in t able 3-1 on page 34 . in this manual, register addresses are given as a hexadecimal increment, relative to the module s base address as shown in the memory map. see also chapter 4, memory map in the arm? cortex?-m3 t echnical reference manual . important: in t able 3-1 on page 34 , addresses not listed are reserved. t able 3-1. memory map a for details on registers, see page ... description end start memory 108 on-chip flash b 0x0000.7fff 0x0000.0000 108 bit-banded on-chip sram c 0x2000.1fff 0x2000.0000 - reserved 0x200f .ffff 0x2010.0000 103 bit-band alias of 0x2000.0000 through 0x200f .ffff 0x22003.ffff 0x2200.0000 - reserved 0x23ff .ffff 0x2204.0000 firm peripherals 195 w atchdog timer 0x4000.0fff 0x4000.0000 125 gpio port a 0x4000.4fff 0x4000.4000 125 gpio port b 0x4000.5fff 0x4000.5000 125 gpio port c 0x4000.6fff 0x4000.6000 125 gpio port d 0x4000.7fff 0x4000.7000 265 ssi0 0x4000.8fff 0x4000.8000 222 uar t0 0x4000.cfff 0x4000.c000 222 uar t1 0x4000.dfff 0x4000.d000 peripherals 304 i2c master 0 0x4002.07ff 0x4002.0000 317 i2c slave 0 0x4002.0fff 0x4002.0800 125 gpio port e 0x4002.7fff 0x4002.4000 168 t imer0 0x4003.0fff 0x4003.0000 168 t imer1 0x4003.1fff 0x4003.1000 168 t imer2 0x4003.2fff 0x4003.2000 326 analog comparators 0x4003.cfff 0x4003.c000 108 flash control 0x400f .dfff 0x400f .d000 56 system control 0x400f .ffff 0x400f .e000 - bit-banded alias of 0x4000.0000 through 0x400f .ffff 0x43ff .ffff 0x4200.0000 private peripheral bus october 01, 2007 34 preliminary memory map
for details on registers, see page ... description end start arm? cortex?-m3 t echnical reference manual instrumentation t race macrocell (itm) 0xe000.0fff 0xe000.0000 data w atchpoint and t race (dwt) 0xe000.1fff 0xe000.1000 flash patch and breakpoint (fpb) 0xe000.2fff 0xe000.2000 reserved 0xe000.dfff 0xe000.3000 nested v ectored interrupt controller (nvic) 0xe000.efff 0xe000.e000 reserved 0xe003.ffff 0xe000.f000 t race port interface unit (tpiu) 0xe004.0fff 0xe004.0000 - reserved 0xe004.1fff 0xe004.1000 - reserved 0xe00f .ffff 0xe004.2000 - reserved for vendor peripherals 0xffff .ffff 0xe010.0000 a. all reserved space returns a bus fault when read or written. b. the unavailable flash will bus fault throughout this range. c. the unavailable sram will bus fault throughout this range. 35 october 01, 2007 preliminary lm3s600 microcontroller
4 interrupts the arm cortex-m3 processor and the nested v ectored interrupt controller (nvic) prioritize and handle all exceptions. all exceptions are handled in handler mode. the processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the interrupt service routine (isr). the vector is fetched in parallel to the state saving, which enables ef ficient interrupt entry . the processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. t able 4-1 on page 36 lists all the exceptions. software can set eight priority levels on seven of these exceptions (system handlers) as well as on 21 interrupts (listed in t able 4-2 on page 37 ). priorities on the system handlers are set with the nvic system handler priority registers. interrupts are enabled through the nvic interrupt set enable register and prioritized with the nvic interrupt priority registers. y ou can also group priorities by splitting priority levels into pre-emption priorities and subpriorities. all the interrupt registers are described in chapter 8, nested v ectored interrupt controller in the arm? cortex?-m3 t echnical reference manual . internally , the highest user-settable priority (0) is treated as fourth priority , after a reset, nmi, and a hard fault. note that 0 is the default priority for all the settable priorities. if you assign the same priority level to two or more interrupts, their hardware priority (the lower the position number) determines the order in which the processor activates them. for example, if both gpio port a and gpio port b are priority level 1, then gpio port a has higher priority . see chapter 5, exceptions and chapter 8, nested v ectored interrupt controller in the arm? cortex?-m3 t echnical reference manual for more information on exceptions and interrupts. note: in t able 4-2 on page 37 interrupts not listed are reserved. t able 4-1. exception t ypes description priority a position exception t ype stack top is loaded from first entry of vector table on reset. - 0 - invoked on power up and warm reset. on first instruction, drops to lowest priority (and then is called the base level of activation). this is asynchronous. -3 (highest) 1 reset cannot be stopped or preempted by any exception but reset. this is asynchronous. an nmi is only producible by software, using the nvic interrupt control state register . -2 2 non-maskable interrupt (nmi) all classes of fault, when the fault cannot activate due to priority or the configurable fault handler has been disabled. this is synchronous. -1 3 hard fault mpu mismatch, including access violation and no match. this is synchronous. the priority of this exception can be changed. settable 4 memory management pre-fetch fault, memory access fault, and other address/memory related faults. this is synchronous when precise and asynchronous when imprecise. y ou can enable or disable this fault. settable 5 bus fault usage fault, such as undefined instruction executed or illegal state transition attempt. this is synchronous. settable 6 usage fault reserved. - 7-10 - system service call with svc instruction. this is synchronous. settable 1 1 svcall october 01, 2007 36 preliminary interrupts
description priority a position exception t ype debug monitor (when not halting). this is synchronous, but only active when enabled. it does not activate if lower priority than the current activation. settable 12 debug monitor reserved. - 13 - pendable request for system service. this is asynchronous and only pended by software. settable 14 pendsv system tick timer has fired. this is asynchronous. settable 15 syst ick asserted from outside the arm cortex-m3 core and fed through the nvic (prioritized). these are all asynchronous. t able 4-2 on page 37 lists the interrupts on the lm3s600 controller . settable 16 and above interrupts a. 0 is the default priority for all the settable priorities. t able 4-2. interrupts description interrupt (bit in interrupt registers) gpio port a 0 gpio port b 1 gpio port c 2 gpio port d 3 gpio port e 4 uar t0 5 uar t1 6 ssi0 7 i2c0 8 w atchdog timer 18 t imer0 a 19 t imer0 b 20 t imer1 a 21 t imer1 b 22 t imer2 a 23 t imer2 b 24 analog comparator 0 25 analog comparator 1 26 analog comparator 2 27 system control 28 flash control 29 reserved 30-31 37 october 01, 2007 preliminary lm3s600 microcontroller
5 jt ag interface the joint t est action group (jt ag) port is an ieee standard that defines a t est access port and boundary scan architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. the t ap , instruction register (ir), and data registers (dr) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. the jt ag port also provides a means of accessing and controlling design-for-test features such as i/o pin observation and control, scan testing, and debugging. the jt ag port is comprised of the standard five pins: trst , tck , tms , tdi , and tdo . data is transmitted serially into the controller on tdi and out of the controller on tdo . the interpretation of this data is dependent on the current state of the t ap controller . for detailed information on the operation of the jt ag port and t ap controller , please refer to the ieee standard 1 149.1-t est access port and boundary-scan architecture . the luminary micro jt ag controller works with the arm jt ag controller built into the cortex-m3 core. this is implemented by multiplexing the tdo outputs from both jt ag controllers. arm jt ag instructions select the arm tdo output while luminary micro jt ag instructions select the luminary micro tdo outputs. the multiplexer is controlled by the luminary micro jt ag controller , which has comprehensive programming for the arm, luminary micro, and unimplemented jt ag instructions. the jt ag module has the following features: ieee 1 149.1-1990 compatible t est access port (t ap) controller four-bit instruction register (ir) chain for storing jt ag instructions ieee standard instructions: C byp ass instruction C idcode instruction C sample/preload instruction C extest instruction C intest instruction arm additional instructions: C ap acc instruction C dp acc instruction C abor t instruction integrated arm serial wire debug (swd) see the arm? cortex?-m3 t echnical reference manual for more information on the arm jt ag controller . october 01, 2007 38 preliminary jt ag interface
5.1 block diagram figure 5-1. jt ag module block diagram 5.2 functional description a high-level conceptual drawing of the jt ag module is shown in figure 5-1 on page 39 . the jt ag module is composed of the t est access port (t ap) controller and serial shift chains with parallel update registers. the t ap controller is a simple state machine controlled by the trst , tck and tms inputs. the current state of the t ap controller depends on the current value of trst and the sequence of values captured on tms at the rising edge of tck . the t ap controller determines when the serial shift chains capture new data, shift data from tdi towards tdo , and update the parallel load registers. the current state of the t ap controller also determines whether the instruction register (ir) chain or one of the data register (dr) chains is being accessed. the serial shift chains with parallel load registers are comprised of a single instruction register (ir) chain and multiple data register (dr) chains. the current instruction loaded in the parallel load register determines which dr chain is captured, shifted, or updated during the sequencing of the t ap controller . some instructions, like extest and intest , operate on data currently in a dr chain and do not capture, shift, or update any of the chains. instructions that are not implemented decode to the byp ass instruction to ensure that the serial path between tdi and tdo is always connected (see t able 5-2 on page 44 for a list of implemented instructions). see jt ag and boundary scan on page 353 for jt ag timing diagrams. 39 october 01, 2007 preliminary lm3s600 microcontroller instr uction register (ir) t ap controller byp ass data register boundar y scan data register idcode data register abor t data register dp a cc data register ap a cc data register trst tck tms tdi tdo cor te x-m3 deb ug p or t
5.2.1 jt ag interface pins the jt ag interface consists of five standard pins: trst , tck , tms , tdi , and tdo . these pins and their associated reset state are given in t able 5-1 on page 40 . detailed information on each pin follows. t able 5-1. jt ag port pins reset state drive v alue drive strength internal pull-down internal pull-up data direction pin name n/a n/a disabled enabled input trst n/a n/a disabled enabled input tck n/a n/a disabled enabled input tms n/a n/a disabled enabled input tdi high-z 2-ma driver disabled enabled output tdo 5.2.1.1 t est reset input ( trst ) the trst pin is an asynchronous active low input signal for initializing and resetting the jt ag t ap controller and associated jt ag circuitry . when trst is asserted, the t ap controller resets to the t est-logic-reset state and remains there while trst is asserted. when the t ap controller enters the t est-logic-reset state, the jt ag instruction register (ir) resets to the default instruction, idcode. by default, the internal pull-up resistor on the trst pin is enabled after reset. changes to the pull-up resistor settings on gpio port b should ensure that the internal pull-up resistor remains enabled on pb7 / trst ; otherwise jt ag communication could be lost. 5.2.1.2 t est clock input (tck) the tck pin is the clock for the jt ag module. this clock is provided so the test logic can operate independently of any other system clocks. in addition, it ensures that multiple jt ag t ap controllers that are daisy-chained together can synchronously communicate serial test data between components. during normal operation, tck is driven by a free-running clock with a nominal 50% duty cycle. when necessary , tck can be stopped at 0 or 1 for extended periods of time. while tck is stopped at 0 or 1, the state of the t ap controller does not change and data in the jt ag instruction and data registers is not lost. by default, the internal pull-up resistor on the tck pin is enabled after reset. this assures that no clocking occurs if the pin is not driven from an external source. the internal pull-up and pull-down resistors can be turned of f to save internal power as long as the tck pin is constantly being driven by an external source. 5.2.1.3 t est mode select (tms) the tms pin selects the next state of the jt ag t ap controller . tms is sampled on the rising edge of tck . depending on the current t ap state and the sampled value of tms , the next state is entered. because the tms pin is sampled on the rising edge of tck , the ieee standard 1 149.1 expects the value on tms to change on the falling edge of tck . holding tms high for five consecutive tck cycles drives the t ap controller state machine to the t est-logic-reset state. when the t ap controller enters the t est-logic-reset state, the jt ag instruction register (ir) resets to the default instruction, idcode. therefore, this sequence can be used as a reset mechanism, similar to asserting trst . the jt ag t est access port state machine can be seen in its entirety in figure 5-2 on page 42 . october 01, 2007 40 preliminary jt ag interface
by default, the internal pull-up resistor on the tms pin is enabled after reset. changes to the pull-up resistor settings on gpio port c should ensure that the internal pull-up resistor remains enabled on pc1/tms ; otherwise jt ag communication could be lost. 5.2.1.4 t est data input (tdi) the tdi pin provides a stream of serial information to the ir chain and the dr chains. tdi is sampled on the rising edge of tck and, depending on the current t ap state and the current instruction, presents this data to the proper shift register chain. because the tdi pin is sampled on the rising edge of tck , the ieee standard 1 149.1 expects the value on tdi to change on the falling edge of tck . by default, the internal pull-up resistor on the tdi pin is enabled after reset. changes to the pull-up resistor settings on gpio port c should ensure that the internal pull-up resistor remains enabled on pc2/tdi ; otherwise jt ag communication could be lost. 5.2.1.5 t est data output (tdo) the tdo pin provides an output stream of serial information from the ir chain or the dr chains. the value of tdo depends on the current t ap state, the current instruction, and the data in the chain being accessed. in order to save power when the jt ag port is not being used, the tdo pin is placed in an inactive drive state when not actively shifting out data. because tdo can be connected to the tdi of another controller in a daisy-chain configuration, the ieee standard 1 149.1 expects the value on tdo to change on the falling edge of tck . by default, the internal pull-up resistor on the tdo pin is enabled after reset. this assures that the pin remains at a constant logic level when the jt ag port is not being used. the internal pull-up and pull-down resistors can be turned of f to save internal power if a high-z output value is acceptable during certain t ap controller states. 5.2.2 jt ag t ap controller the jt ag t ap controller state machine is shown in figure 5-2 on page 42 . the t ap controller state machine is reset to the t est-logic-reset state on the assertion of a power-on-reset (por) or the assertion of trst . asserting the correct sequence on the tms pin allows the jt ag module to shift in new instructions, shift in data, or idle during extended testing sequences. for detailed information on the function of the t ap controller and the operations that occur in each state, please refer to ieee standard 1 149.1 . 41 october 01, 2007 preliminary lm3s600 microcontroller
figure 5-2. t est access port state machine 5.2.3 shift registers the shift registers consist of a serial shift register chain and a parallel load register . the serial shift register chain samples specific information during the t ap controller s capture states and allows this information to be shifted out of tdo during the t ap controller s shift states. while the sampled data is being shifted out of the chain on tdo , new data is being shifted into the serial shift register on tdi . this new data is stored in the parallel load register during the t ap controller s upda te states. each of the shift registers is discussed in detail in register descriptions on page 44 . 5.2.4 operational considerations there are certain operational considerations when using the jt ag module. because the jt ag pins can be programmed to be gpios, board configuration and reset conditions on these pins must be considered. in addition, because the jt ag module has integrated arm serial wire debug, the method for switching between these two operational modes is described below . october 01, 2007 42 preliminary jt ag interface t est logic reset run t est idle select dr scan select ir scan capture dr capture ir shift dr shift ir exit 1 dr exit 1 ir exit 2 dr exit 2 ir pause dr pause ir update dr update ir 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
5.2.4.1 gpio functionality when the controller is reset with either a por or rst , the jt ag port pins default to their jt ag configurations. the default configuration includes enabling the pull-up resistors (setting gpiopur to 1 for pb7 and pc[3:0] ) and enabling the alternate hardware function (setting gpioafsel to 1 for pb7 and pc[3:0] ) on the jt ag pins. it is possible for software to configure these pins as gpios after reset by writing 0s to pb7 and pc[3:0] in the gpioafsel register . if the user does not require the jt ag port for debugging or board-level testing, this provides five more gpios for use in the design. caution C if the jt ag pins ar e used as gpios in a design, pb7 and pc2 cannot have external pull-down r esistors connected to both of them at the same time. if both pins ar e pulled low during r eset, the contr oller has unpr edictable behavior . if this happens, r emove one or both of the pull-down r esistors, and apply rst or power-cycle the part. in addition, it is possible to cr eate a softwar e sequence that pr events the debugger fr om connecting to the stellaris ? micr ocontr oller . if the pr ogram code loaded into fash immediately changes the jt ag pins to their gpio functionality , the debugger may not have enough time to connect and halt the contr oller befor e the jt ag pin functionality switches. this may lock the debugger out of the part. this can be avoided with a softwar e r outine that r estor es jt ag functionality based on an external or softwar e trigger . 5.2.4.2 arm serial w ire debug (swd) in order to seamlessly integrate the arm serial wire debug (swd) functionality , a serial-wire debugger must be able to connect to the cortex-m3 core without having to perform, or have any knowledge of, jt ag cycles. this is accomplished with a swd preamble that is issued before the swd session begins. the preamble used to enable the swd interface of the swj-dp module starts with the t ap controller in the t est-logic-reset state. from here, the preamble sequences the t ap controller through the following states: run t est idle, select dr, select ir, capture ir, exit1 ir, update ir, run t est idle, select dr, select ir, capture ir, exit1 ir, update ir, run t est idle, select dr, select ir, and t est-logic-reset states. stepping through the jt ag t ap instruction register (ir) load sequences of the t ap state machine twice without shifting in a new instruction enables the swd interface and disables the jt ag interface. for more information on this operation and the swd interface, see the arm? cortex?-m3 t echnical reference manual and the arm? coresight t echnical reference manual . because this sequence is a valid series of jt ag operations that could be issued, the arm jt ag t ap controller is not fully compliant to the ieee standard 1 149.1 . this is the only instance where the arm jt ag t ap controller does not meet full compliance with the specification. due to the low probability of this sequence occurring during normal operation of the t ap controller , it should not af fect normal performance of the jt ag interface. 5.3 initialization and configuration after a power-on-reset or an external reset ( rst ), the jt ag pins are automatically configured for jt ag communication. no user-defined initialization or configuration is needed. however , if the user application changes these pins to their gpio function, they must be configured back to their jt ag functionality before jt ag communication can be restored. this is done by enabling the five jt ag pins ( pb7 and pc[3:0] ) for their alternate function using the gpioafsel register . 43 october 01, 2007 preliminary lm3s600 microcontroller
5.4 register descriptions there are no apb-accessible registers in the jt ag t ap controller or shift register chains. the registers within the jt ag controller are all accessed serially through the t ap controller . the registers can be broken down into two main categories: instruction registers and data registers. 5.4.1 instruction register (ir) the jt ag t ap instruction register (ir) is a four-bit serial scan chain with a parallel load register connected between the jt ag tdi and tdo pins. when the t ap controller is placed in the correct states, bits can be shifted into the instruction register . once these bits have been shifted into the chain and updated, they are interpreted as the current instruction. the decode of the instruction register bits is shown in t able 5-2 on page 44 . a detailed explanation of each instruction, along with its associated data register , follows. t able 5-2. jt ag instruction register commands description instruction ir[3:0] drives the values preloaded into the boundary scan chain by the sample/preload instruction onto the pads. extest 0000 drives the values preloaded into the boundary scan chain by the sample/preload instruction into the controller . intest 0001 captures the current i/o values and shifts the sampled values out of the boundary scan chain while new preload data is shifted in. sample / preload 0010 shifts data into the arm debug port abort register . abor t 1000 shifts data into and out of the arm dp access register . dp acc 1010 shifts data into and out of the arm ac access register . ap acc 101 1 loads manufacturing information defined by the ieee standard 1 149.1 into the idcode chain and shifts it out. idcode 1 1 10 connects tdi to tdo through a single shift register chain. byp ass 1 1 1 1 defaults to the byp ass instruction to ensure that tdi is always connected to tdo . reserved all others 5.4.1.1 extest instruction the extest instruction does not have an associated data register chain. the extest instruction uses the data that has been preloaded into the boundary scan data register using the sample/preload instruction. when the extest instruction is present in the instruction register , the preloaded data in the boundary scan data register associated with the outputs and output enables are used to drive the gpio pads rather than the signals coming from the core. this allows tests to be developed that drive known values out of the controller , which can be used to verify connectivity . 5.4.1.2 intest instruction the intest instruction does not have an associated data register chain. the intest instruction uses the data that has been preloaded into the boundary scan data register using the sample/preload instruction. when the intest instruction is present in the instruction register , the preloaded data in the boundary scan data register associated with the inputs are used to drive the signals going into the core rather than the signals coming from the gpio pads. this allows tests to be developed that drive known values into the controller , which can be used for testing. it is important to note that although the rst input pin is on the boundary scan data register chain, it is only observable. october 01, 2007 44 preliminary jt ag interface
5.4.1.3 sample/preload instruction the sample/preload instruction connects the boundary scan data register chain between tdi and tdo . this instruction samples the current state of the pad pins for observation and preloads new test data. each gpio pad has an associated input, output, and output enable signal. when the t ap controller enters the capture dr state during this instruction, the input, output, and output-enable signals to each of the gpio pads are captured. these samples are serially shifted out of tdo while the t ap controller is in the shift dr state and can be used for observation or comparison in various tests. while these samples of the inputs, outputs, and output enables are being shifted out of the boundary scan data register , new data is being shifted into the boundary scan data register from tdi . once the new data has been shifted into the boundary scan data register , the data is saved in the parallel load registers when the t ap controller enters the update dr state. this update of the parallel load register preloads data into the boundary scan data register that is associated with each input, output, and output enable. this preloaded data can be used with the extest and intest instructions to drive data into or out of the controller . please see boundary scan data register on page 46 for more information. 5.4.1.4 abort instruction the abor t instruction connects the associated abor t data register chain between tdi and tdo . this instruction provides read and write access to the abor t register of the arm debug access port (dap). shifting the proper data into this data register clears various error bits or initiates a dap abort of a previous request. please see the abor t data register on page 47 for more information. 5.4.1.5 dp acc instruction the dp acc instruction connects the associated dp acc data register chain between tdi and tdo . this instruction provides read and write access to the dp acc register of the arm debug access port (dap). shifting the proper data into this register and reading the data output from this register allows read and write access to the arm debug and status registers. please see dp acc data register on page 47 for more information. 5.4.1.6 ap acc instruction the ap acc instruction connects the associated ap acc data register chain between tdi and tdo . this instruction provides read and write access to the ap acc register of the arm debug access port (dap). shifting the proper data into this register and reading the data output from this register allows read and write access to internal components and buses through the debug port. please see ap acc data register on page 47 for more information. 5.4.1.7 idcode instruction the idcode instruction connects the associated idcode data register chain between tdi and tdo . this instruction provides information on the manufacturer , part number , and version of the arm core. this information can be used by testing equipment and debuggers to automatically configure their input and output data streams. idcode is the default instruction that is loaded into the jt ag instruction register when a power-on-reset (por) is asserted, trst is asserted, or the t est-logic-reset state is entered. please see idcode data register on page 46 for more information. 45 october 01, 2007 preliminary lm3s600 microcontroller
5.4.1.8 byp ass instruction the byp ass instruction connects the associated byp ass data register chain between tdi and tdo . this instruction is used to create a minimum length serial path between the tdi and tdo ports. the byp ass data register is a single-bit shift register . this instruction improves test ef ficiency by allowing components that are not needed for a specific test to be bypassed in the jt ag scan chain by loading them with the byp ass instruction. please see byp ass data register on page 46 for more information. 5.4.2 data registers the jt ag module contains six data registers. these include: idcode, byp ass, boundary scan, ap acc, dp acc, and abor t serial data register chains. each of these data registers is discussed in the following sections. 5.4.2.1 idcode data register the format for the 32-bit idcode data register defined by the ieee standard 1 149.1 is shown in figure 5-3 on page 46 . the standard requires that every jt ag-compliant device implement either the idcode instruction or the byp ass instruction as the default instruction. the lsb of the idcode data register is defined to be a 1 to distinguish it from the byp ass instruction, which has an lsb of 0. this allows auto configuration test tools to determine which instruction is the default instruction. the major uses of the jt ag port are for manufacturer testing of component assembly , and program development and debug. t o facilitate the use of auto-configuration debug tools, the idcode instruction outputs a value of 0x1ba00477. this value indicates an arm cortex-m3, v ersion 1 processor . this allows the debuggers to automatically configure themselves to work correctly with the cortex-m3 during debug. figure 5-3. idcode register format 5.4.2.2 byp ass data register the format for the 1-bit byp ass data register defined by the ieee standard 1 149.1 is shown in figure 5-4 on page 46 . the standard requires that every jt ag-compliant device implement either the byp ass instruction or the idcode instruction as the default instruction. the lsb of the byp ass data register is defined to be a 0 to distinguish it from the idcode instruction, which has an lsb of 1. this allows auto configuration test tools to determine which instruction is the default instruction. figure 5-4. byp ass register format 5.4.2.3 boundary scan data register the format of the boundary scan data register is shown in figure 5-5 on page 47 . each gpio pin, in a counter-clockwise direction from the jt ag port pins, is included in the boundary scan data register . each gpio pin has three associated digital signals that are included in the chain. these october 01, 2007 46 preliminary jt ag interface
signals are input, output, and output enable, and are arranged in that order as can be seen in the figure. in addition to the gpio pins, the controller reset pin, rst , is included in the chain. because the reset pin is always an input, only the input signal is included in the data register chain. when the boundary scan data register is accessed with the sample/preload instruction, the input, output, and output enable from each digital pad are sampled and then shifted out of the chain to be verified. the sampling of these values occurs on the rising edge of tck in the capture dr state of the t ap controller . while the sampled data is being shifted out of the boundary scan chain in the shift dr state of the t ap controller , new data can be preloaded into the chain for use with the extest and intest instructions. these instructions either force data out of the controller , with the extest instruction, or into the controller , with the intest instruction. figure 5-5. boundary scan register format for detailed information on the order of the input, output, and output enable bits for each of the gpio ports, please refer to the stellaris ? family boundary scan description language (bsdl) files, downloadable from www .luminarymicro.com. 5.4.2.4 ap acc data register the format for the 35-bit ap acc data register defined by arm is described in the arm? cortex?-m3 t echnical reference manual . 5.4.2.5 dp acc data register the format for the 35-bit dp acc data register defined by arm is described in the arm? cortex?-m3 t echnical reference manual . 5.4.2.6 abort data register the format for the 35-bit abor t data register defined by arm is described in the arm? cortex?-m3 t echnical reference manual . 47 october 01, 2007 preliminary lm3s600 microcontroller o t d o t d i o i n e u t o o i n e u t o o i n e u t o o i n e u t i n ... ... r s t g p i o p b 6 g p i o m g p i o m + 1 g p i o n
6 system control system control determines the overall operation of the device. it provides information about the device, controls the clocking to the core and individual peripherals, and handles reset detection and reporting. 6.1 functional description the system control module provides the following capabilities: device identification, see device identification on page 48 local control, such as reset (see reset control on page 48 ), power (see power control on page 51 ) and clock control (see clock control on page 51 ) system control (run, sleep, and deep-sleep modes), see system control on page 54 6.1.1 device identification seven read-only registers provide software with information on the microcontroller , such as version, part number , sram size, flash size, and other features. see the did0 , did1 , and dc0 - dc4 registers. 6.1.2 reset control this section discusses aspects of hardware functions during reset as well as system software requirements following the reset sequence. 6.1.2.1 reset sources the controller has six sources of reset: 1. external reset input pin ( rst ) assertion, see rst pin assertion on page 48 . 2. power-on reset (por), see power-on reset (por) on page 49 . 3. internal brown-out (bor) detector , see brown-out reset (bor) on page 49 . 4. software-initiated reset (with the software reset registers), see software reset on page 50 . 5. a watchdog timer reset condition violation, see w atchdog t imer reset on page 51 . 6. internal low drop-out (ldo) regulator output after a reset, the reset cause (resc) register is set with the reset cause. the bits in this register are sticky and maintain their state across multiple reset sequences,except when an external reset is the cause, and then all the other bits in the resc register are cleared. note: the main oscillator is used for external resets and power-on resets; the internal oscillator is used during the internal process by internal reset and clock verification circuitry . 6.1.2.2 rst pin assertion the external reset pin ( rst ) resets the controller . this resets the core and all the peripherals except the jt ag t ap controller (see jt ag interface on page 38 ). the external reset sequence is as follows: october 01, 2007 48 preliminary system control
1. the external reset pin ( rst ) is asserted and then de-asserted. 2. after rst is de-asserted, the main crystal oscillator is allowed to settle and there is an internal main oscillator counter that takes from 15-30 ms to account for this. during this time, internal reset to the rest of the controller is held active. 3. the internal reset is released and the core fetches and loads the initial stack pointer , the initial program counter , the first instruction designated by the program counter , and begins execution. the external reset timing is shown in figure 18-9 on page 356 . 6.1.2.3 power-on reset (por) the power-on reset (por) circuitry detects a rise in power-supply voltage (v dd ) and generates an on-chip reset pulse. t o use the on-chip circuitry , the rst input needs to be connected to the power supply (v dd ) through a pull-up resistor (1k to 10k ?). the device must be operating within the specified operating parameters at the point when the on-chip power-on reset pulse is complete. the specified operating parameters include supply voltage, frequency , temperature, and so on. if the operating conditions are not met at the point of por end, the stellaris ? controller does not operate correctly . in this case, the reset must be extended using external circuitry . the rst input may be used with the circuit as shown in figure 6-1 on page 49 . figure 6-1. external circuitry to extend reset the r 1 and c 1 components define the power-on delay . the r 2 resistor mitigates any leakage from the rst input. the diode (d 1 ) discharges c 1 rapidly when the power supply is turned of f. the power-on reset sequence is as follows: 1. the controller waits for the later of external reset ( rst ) or internal por to go inactive. 2. after the resets are inactive, the main crystal oscillator is allowed to settle and there is an internal main oscillator counter that takes from 15-30 ms to account for this. during this time, internal reset to the rest of the controller is held active. 3. the internal reset is released and the core fetches and loads the initial stack pointer , the initial program counter , the first instruction designated by the program counter , and begins execution. the internal por is only active on the initial power-up of the controller . the power-on reset timing is shown in figure 18-10 on page 356 . note: the power-on reset also resets the jt ag controller . an external reset does not. 6.1.2.4 brown-out reset (bor) a drop in the input voltage resulting in the assertion of the internal brown-out detector can be used to reset the controller . this is initially disabled and may be enabled by software. 49 october 01, 2007 preliminary lm3s600 microcontroller r 1 c 1 r 2 rst stellaris d 1
the system provides a brown-out detection circuit that triggers if the power supply (v dd ) drops below a brown-out threshold voltage (v bth ). the circuit is provided to guard against improper operation of logic and peripherals that operate of f the power supply voltage (v dd ) and not the ldo voltage. if a brown-out condition is detected, the system may generate a controller interrupt or a system reset. the bor circuit has a digital filter that protects against noise-related detection for the interrupt condition. this feature may be optionally enabled. brown-out resets are controlled with the power-on and brown-out reset control (pborctl) register . the borior bit in the pborctl register must be set for a brown-out condition to trigger a reset. the brown-out reset sequence is as follows: 1. when v dd drops below v bth , an internal bor condition is set. 2. if the borwt bit in the pborctl register is set and borior is not set, the bor condition is resampled again, after a delay specified by bortim , to determine if the original condition was caused by noise. if the bor condition is not met the second time, then no further action is taken. 3. if the bor condition exists, an internal reset is asserted. 4. the internal reset is released and the controller fetches and loads the initial stack pointer , the initial program counter , the first instruction designated by the program counter , and begins execution. 5. the internal bor condition is reset after 500 s to prevent another bor condition from being set before software has a chance to investigate the original cause. the internal brown-out reset timing is shown in figure 18-1 1 on page 357 . 6.1.2.5 software reset software can reset a specific peripheral or generate a reset to the entire system . peripherals can be individually reset by software via three registers that control reset signals to each peripheral (see the srcrn registers). if the bit position corresponding to a peripheral is set and subsequently cleared, the peripheral is reset. the encoding of the reset registers is consistent with the encoding of the clock gating control for peripherals and on-chip functions (see system control on page 54 ). note that all reset signals for all clocks of the specified unit are asserted as a result of a software-initiated reset. the entire system can be reset by software by setting the sysresetreq bit in the cortex-m3 application interrupt and reset control register resets the entire system including the core. the software-initiated system reset sequence is as follows: 1. a software system reset is initiated by writing the sysresetreq bit in the arm cortex-m3 application interrupt and reset control register . 2. an internal reset is asserted. 3. the internal reset is deasserted and the controller loads from memory the initial stack pointer , the initial program counter , and the first instruction designated by the program counter , and then begins execution. the software-initiated system reset timing is shown in figure 18-12 on page 357 . october 01, 2007 50 preliminary system control
6.1.2.6 w atchdog t imer reset the watchdog timer module's function is to prevent system hangs. the watchdog timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. after the first time-out event, the 32-bit counter is reloaded with the value of the w atchdog t imer load (wdtload) register , and the timer resumes counting down from that value. if the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled, the watchdog timer asserts its reset signal to the system. the watchdog timer reset sequence is as follows: 1. the watchdog timer times out for the second time without being serviced. 2. an internal reset is asserted. 3. the internal reset is released and the controller loads from memory the initial stack pointer , the initial program counter , the first instruction designated by the program counter , and begins execution. the watchdog reset timing is shown in figure 18-13 on page 357 . 6.1.2.7 low drop-out a reset can be initiated when the internal low drop-out (ldo) regulator output goes unregulated. this is initially disabled and may be enabled by software. ldo is controlled with the ldo power control (ldopctl) register . the ldo reset sequence is as follows: 1. ldo goes unregulated and the ldoarst bit in the ldoarst register is set. 2. an internal reset is asserted. 3. the internal reset is released and the controller fetches and loads the initial stack pointer , the initial program counter , the first instruction designated by the program counter , and begins execution. the ldo reset timing is shown in figure 18-14 on page 357 . 6.1.3 power control the stellaris ? microcontroller provides an integrated ldo regulator that is used to provide power to the majority of the controller's internal logic. the ldo regulator provides software a mechanism to adjust the regulated value, in small increments (vstep), over the range of 2.25 v to 2.75 v (inclusive)or 2.5 v 10%. the adjustment is made by changing the value of the vadj field in the ldo power control (ldopctl) register . 6.1.4 clock control system control determines the control of clocks in this part. 6.1.4.1 fundamental clock sources there are two clock sources for use in the device: internal oscillator (iosc): the internal oscillator is an on-chip clock source. it does not require the use of any external components. the frequency of the internal oscillator is 12 mhz 30%. 51 october 01, 2007 preliminary lm3s600 microcontroller
applications that do not depend on accurate clock sources may use this clock source to reduce system cost. main oscillator: the main oscillator provides a frequency-accurate clock source by one of two means: an external single-ended clock source is connected to the osc0 input pin, or an external crystal is connected across the osc0 input and osc1 output pins. the crystal value allowed depends on whether the main oscillator is used as the clock reference source to the pll. if so, the crystal must be one of the supported frequencies between 3.579545 mhz through 8.192 mhz (inclusive). if the pll is not being used, the crystal may be any one of the supported frequencies between 1 mhz and 8.192 mhz. the single-ended clock source range is from dc through the specified speed of the device. the supported crystals are listed in the xtal bit in the rcc register (see page 66 ). the internal system clock (sysclk), is derived from any of the two sources plus two others: the output of the internal pll, and the internal oscillator divided by four (3 mhz 30%). the frequency of the pll clock reference must be in the range of 3.579545 mhz to 8.192 mhz (inclusive). nearly all of the control for the clocks is provided by the run-mode clock configuration (rcc) register . figure 6-2 on page 52 shows the logic for the main clock tree. the peripheral blocks are driven by the system clock signal and can be programmatically enabled/disabled. figure 6-2. main clock t ree 6.1.4.2 crystal configuration for the main oscillator (mosc) the main oscillator supports the use of a select number of crystals. if the main oscillator is used by the pll as a reference clock, the supported range of crystals is 3.579545 to 8.192 mhz, otherwise, the range of supported crystals is 1 to 8.192 mhz. the xtal bit in the rcc register (see page 66 ) describes the available crystal choices and default programming values. software configures the rcc register xtal field with the crystal number . if the pll is used in the design, the xtal field value is internally translated to the pll settings. october 01, 2007 52 preliminary system control main osc 1 - 8 mhz internal osc 12 mhz 4 oscsrc a osc1 osc2 pll ( 200 mhz output ) byp ass a sysdiv a usesysdiv a system clock oen a xt al a pwrdn a a. these are bit fields within the run - mode clock configuration ( rcc ) register .
6.1.4.3 pll frequency configuration the pll is disabled by default during power-on reset and is enabled later by software if required. software configures the pll input reference clock source, specifies the output divisor to set the system clock frequency , and enables the pll to drive the output. if the main oscillator provides the clock reference to the pll, the translation provided by hardware and used to program the pll is available for software in the xt al to pll t ranslation (pllcfg) register (see page 70 ). the internal translation provides a translation within 1% of the targeted pll vco frequency . the xtal bit in the rcc register (see page 66 ) describes the available crystal choices and default programming of the pllcfg register . the crystal number is written into the xtal field of the run-mode clock configuration (rcc) register . any time the xtal field changes, the new settings are translated and the internal pll settings are updated. 6.1.4.4 pll modes the pll has two modes of operation: normal and power-down normal: the pll multiplies the input clock reference and drives the output. power-down: most of the pll internal circuitry is disabled and the pll does not drive the output. the modes are programmed using the rcc register fields (see page 66 ). 6.1.4.5 pll operation if the pll configuration is changed, the pll output frequency is unstable until it reconverges (relocks) to the new setting. the time between the configuration change and relock is t ready (see t able 18-6 on page 350 ). during this time, the pll is not usable as a clock reference. the pll is changed by one of the following: change to the xtal value in the rcc registerwrites of the same value do not cause a relock. change in the pll from power-down to normal mode. a counter is defined to measure the t ready requirement. the counter is clocked by the main oscillator . the range of the main oscillator has been taken into account and the down counter is set to 0x1200 (that is, ~600 s at an 8.192 mhz external oscillator clock). hardware is provided to keep the pll from being used as a system clock until the t ready condition is met after one of the two changes above. it is the user's responsibility to have a stable clock source (like the main oscillator) before the rcc register is switched to use the pll. 6.1.4.6 clock v erification t imers there are three identical clock verification circuits that can be enabled though software. the circuit checks the faster clock by a slower clock using timers: the main oscillator checks the pll. the main oscillator checks the internal oscillator . the internal oscillator divided by 64 checks the main oscillator . if the verification timer function is enabled and a failure is detected, the main clock tree is immediately switched to a working clock and an interrupt is generated to the controller . software can then 53 october 01, 2007 preliminary lm3s600 microcontroller
determine the course of action to take. the actual failure indication and clock switching does not clear without a write to the clkvclr register , an external reset, or a por reset. the clock verification timers are controlled by the pllver , ioscver , and moscver bits in the rcc register . 6.1.5 system control for power-savings purposes, the rcgcn , scgcn , and dcgcn registers control the clock gating logic for each peripheral or block in the system while the controller is in run, sleep, and deep-sleep mode, respectively . the dc1 , dc2 and dc4 registers act as a write mask for the rcgcn , scgcn , and dcgcn registers. in run mode, the controller is actively executing code. in sleep mode, the clocking of the device is unchanged but the controller no longer executes code (and is no longer clocked). in deep-sleep mode, the clocking of the device may change (depending on the run mode clock configuration) and the controller no longer executes code (and is no longer clocked). an interrupt returns the device to run mode from one of the sleep modes. each mode is described in more detail in this section. there are four levels of operation for the device defined as: run mode. run mode provides normal operation of the processor and all of the peripherals that are currently enabled by the rcgcn registers. the system clock can be any of the available clock sources including the pll. sleep mode. sleep mode is entered by the cortex-m3 core executing a wfi (wait for interrupt) instruction. any properly configured interrupt event in the system will bring the processor back into run mode. see the system control nvic section of the arm? cortex?-m3 t echnical reference manual for more details. in sleep mode, the cortex-m3 processor core and the memory subsystem are not clocked. peripherals are clocked that are enabled in the scgcn register when auto-clock gating is enabled (see the rcc register) or the rcgcn register when the auto-clock gating is disabled. the system clock has the same source and frequency as that during run mode. deep-sleep mode. deep-sleep mode is entered by first writing the deep sleep enable bit in the arm cortex-m3 nvic system control register and then executing a wfi instruction. any properly configured interrupt event in the system will bring the processor back into run mode. see the system control nvic section of the arm? cortex?-m3 t echnical reference manual for more details. the cortex-m3 processor core and the memory subsystem are not clocked. peripherals are clocked that are enabled in the dcgcn register when auto-clock gating is enabled (see the rcc register) or the rcgcn register when auto-clock gating is disabled. the system clock source is the main oscillator by default or the internal oscillator specified in the dslpclkcfg register if one is enabled. when the dslpclkcfg register is used, the internal oscillator is powered up, if necessary , and the main oscillator is powered down. if the pll is running at the time of the wfi instruction, hardware will power the pll down and override the sysdiv field of the active rcc register to be /16 or /64, respectively . when the deep-sleep exit event occurs, hardware brings the system clock back to the source and frequency it had at the onset of deep-sleep mode before enabling the clocks that had been stopped during the deep-sleep duration. 6.2 initialization and configuration the pll is configured using direct register writes to the rcc register . the steps required to successfully change the pll-based system clock are: october 01, 2007 54 preliminary system control
1. bypass the pll and system clock divider by setting the bypass bit and clearing the usesys bit in the rcc register . this configures the system to run of f a raw clock source (using the main oscillator or internal oscillator) and allows for the new pll configuration to be validated before switching the system clock to the pll. 2. select the crystal value ( xtal ) and oscillator source ( oscsrc ), and clear the pwrdn and oen bits in rcc . setting the xtal field automatically pulls valid pll configuration data for the appropriate crystal, and clearing the pwrdn and oen bits powers and enables the pll and its output. 3. select the desired system divider ( sysdiv ) in rcc and set the usesys bit in rcc . the sysdiv field determines the system frequency for the microcontroller . 4. w ait for the pll to lock by polling the plllris bit in the raw interrupt status (ris ) register . 5. enable use of the pll by clearing the bypass bit in rcc . note: if the bypass bit is cleared before the pll locks, it is possible to render the device unusable. 6.3 register map t able 6-1 on page 55 lists the system control registers, grouped by function. the of fset listed is a hexadecimal increment to the register s address, relative to the system control base address of 0x400f .e000. note: spaces in the system control register space that are not used are reserved for future or internal use by luminary micro, inc. software should not modify any reserved memory address. t able 6-1. system control register map see page description reset t ype name offset 57 device identification 0 - ro did0 0x000 74 device identification 1 - ro did1 0x004 76 device capabilities 0 0x001f .000f ro dc0 0x008 77 device capabilities 1 0x0000.309f ro dc1 0x010 79 device capabilities 2 0x0707.1013 ro dc2 0x014 81 device capabilities 3 0x3f00.7fc0 ro dc3 0x018 83 device capabilities 4 0x0000.001f ro dc4 0x01c 59 power-on and brown-out reset control 0x0000.7ffd r/w pborctl 0x030 60 ldo power control 0x0000.0000 r/w ldopctl 0x034 99 software reset control 0 0x00000000 r/w srcr0 0x040 100 software reset control 1 0x00000000 r/w srcr1 0x044 102 software reset control 2 0x00000000 r/w srcr2 0x048 61 raw interrupt status 0x0000.0000 ro ris 0x050 62 interrupt mask control 0x0000.0000 r/w imc 0x054 55 october 01, 2007 preliminary lm3s600 microcontroller
see page description reset t ype name offset 64 masked interrupt status and clear 0x0000.0000 r/w1c misc 0x058 65 reset cause - r/w resc 0x05c 66 run-mode clock configuration 0x07a0.3ad1 r/w rcc 0x060 70 xt al to pll t ranslation - ro pllcfg 0x064 84 run mode clock gating control register 0 0x00000040 r/w rcgc0 0x100 87 run mode clock gating control register 1 0x00000000 r/w rcgc1 0x104 93 run mode clock gating control register 2 0x00000000 r/w rcgc2 0x108 85 sleep mode clock gating control register 0 0x00000040 r/w scgc0 0x1 10 89 sleep mode clock gating control register 1 0x00000000 r/w scgc1 0x1 14 95 sleep mode clock gating control register 2 0x00000000 r/w scgc2 0x1 18 86 deep sleep mode clock gating control register 0 0x00000040 r/w dcgc0 0x120 91 deep sleep mode clock gating control register 1 0x00000000 r/w dcgc1 0x124 97 deep sleep mode clock gating control register 2 0x00000000 r/w dcgc2 0x128 71 deep sleep clock configuration 0x0780.0000 r/w dslpclkcfg 0x144 72 clock v erification clear 0x0000.0000 r/w clkvclr 0x150 73 allow unregulated ldo to reset the part 0x0000.0000 r/w ldoarst 0x160 6.4 register descriptions all addresses given are relative to the system control base address of 0x400f .e000. october 01, 2007 56 preliminary system control
register 1: device identification 0 (did0), offset 0x000 this register identifies the version of the device. device identification 0 (did0) base 0x400f .e000 of fset 0x000 t ype ro, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ver reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 minor major ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype - - - - - - - - - - - - - - - - reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31 did0 v ersion this field defines the did0 register format version. the version number is numeric. the value of the ver field is encoded as follows: description v alue initial did0 register format definition for stellaris? sandstorm-class devices. 0x0 0x0 ro ver 30:28 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 27:16 major revision this field specifies the major revision number of the device. the major revision reflects changes to base layers of the design. the major revision number is indicated in the part number as a letter (a for first revision, b for second, and so on). this field is encoded as follows: description v alue revision a (initial device) 0x0 revision b (first base layer revision) 0x1 revision c (second base layer revision) 0x2 and so on. - ro major 15:8 57 october 01, 2007 preliminary lm3s600 microcontroller
description reset t ype name bit/field minor revision this field specifies the minor revision number of the device. the minor revision reflects changes to the metal layers of the design. the minor field value is reset when the major field is changed. this field is numeric and is encoded as follows: description v alue initial device, or a major revision update. 0x0 first metal layer change. 0x1 second metal layer change. 0x2 and so on. - ro minor 7:0 october 01, 2007 58 preliminary system control
register 2: power-on and brown-out reset control (pborctl), offset 0x030 this register is responsible for controlling reset conditions after initial power-on reset. power-on and brown-out reset control (pborctl) base 0x400f .e000 of fset 0x030 t ype r/w , reset 0x0000.7ffd 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 bor wt borior bor tim r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:16 bor t ime delay this field specifies the number of internal oscillator clocks delayed before the bor output is resampled if the borwt bit is set. the width of this field is derived by the t bor width of 500 s and the internal oscillator (iosc) frequency of 12 mhz 30%. at +30%, the counter value has to exceed 7,800. 0x1fff r/w bor tim 15:2 bor interrupt or reset this bit controls how a bor event is signaled to the controller . if set, a reset is signaled. otherwise, an interrupt is signaled. 0 r/w borior 1 bor w ait and check for noise this bit specifies the response to a brown-out signal assertion if borior is not set. if borwt is set to 1 and borior is cleared to 0, the controller waits bortim iosc periods and resamples the bor output. if still asserted, a bor interrupt is signalled. if no longer asserted, the initial assertion is suppressed (attributable to noise). if borwt is 0, bor assertions do not resample the output and any condition is reported immediately if enabled. 1 r/w bor wt 0 59 october 01, 2007 preliminary lm3s600 microcontroller
register 3: ldo power control (ldopctl), offset 0x034 the vadj field in this register adjusts the on-chip output voltage (v out ). ldo power control (ldopctl) base 0x400f .e000 of fset 0x034 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 v adj reserved r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:6 ldo output v oltage this field sets the on-chip output voltage. the programming values for the vadj field are provided below . v out (v) v alue 2.50 0x00 2.45 0x01 2.40 0x02 2.35 0x03 2.30 0x04 2.25 0x05 reserved 0x06-0x3f 2.75 0x1b 2.70 0x1c 2.65 0x1d 2.60 0x1e 2.55 0x1f 0x0 r/w v adj 5:0 october 01, 2007 60 preliminary system control
register 4: raw interrupt status (ris), offset 0x050 central location for system control raw interrupts. these are set and cleared by hardware. raw interrupt status (ris) base 0x400f .e000 of fset 0x050 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pllfris borris ldoris mofris iofris clris plllris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:7 pll lock raw interrupt status this bit is set when the pll t ready t imer asserts. 0 ro plllris 6 current limit raw interrupt status this bit is set if the ldo s cle output asserts. 0 ro clris 5 internal oscillator fault raw interrupt status this bit is set if an internal oscillator fault is detected. 0 ro iofris 4 main oscillator fault raw interrupt status this bit is set if a main oscillator fault is detected. 0 ro mofris 3 ldo power unregulated raw interrupt status this bit is set if a ldo voltage is unregulated. 0 ro ldoris 2 brown-out reset raw interrupt status this bit is the raw interrupt status for any brown-out conditions. if set, a brown-out condition is currently active. this is an unregistered signal from the brown-out detection circuit. an interrupt is reported if the borim bit in the imc register is set and the borior bit in the pborctl register is cleared. 0 ro borris 1 pll fault raw interrupt status this bit is set if a pll fault is detected (stops oscillating). 0 ro pllfris 0 61 october 01, 2007 preliminary lm3s600 microcontroller
register 5: interrupt mask control (imc), offset 0x054 central location for system control interrupt masks. interrupt mask control (imc) base 0x400f .e000 of fset 0x054 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pllfim borim ldoim mofim iofim clim plllim reserved r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:7 pll lock interrupt mask this bit specifies whether a current limit detection is promoted to a controller interrupt. if set, an interrupt is generated if plllris in ris is set; otherwise, an interrupt is not generated. 0 r/w plllim 6 current limit interrupt mask this bit specifies whether a current limit detection is promoted to a controller interrupt. if set, an interrupt is generated if clris is set; otherwise, an interrupt is not generated. 0 r/w clim 5 internal oscillator fault interrupt mask this bit specifies whether an internal oscillator fault detection is promoted to a controller interrupt. if set, an interrupt is generated if iofris is set; otherwise, an interrupt is not generated. 0 r/w iofim 4 main oscillator fault interrupt mask this bit specifies whether a main oscillator fault detection is promoted to a controller interrupt. if set, an interrupt is generated if mofris is set; otherwise, an interrupt is not generated. 0 r/w mofim 3 ldo power unregulated interrupt mask this bit specifies whether an ldo unregulated power situation is promoted to a controller interrupt. if set, an interrupt is generated if ldoris is set; otherwise, an interrupt is not generated. 0 r/w ldoim 2 brown-out reset interrupt mask this bit specifies whether a brown-out condition is promoted to a controller interrupt. if set, an interrupt is generated if borris is set; otherwise, an interrupt is not generated. 0 r/w borim 1 october 01, 2007 62 preliminary system control
description reset t ype name bit/field pll fault interrupt mask this bit specifies whether a pll fault detection is promoted to a controller interrupt. if set, an interrupt is generated if pllfris is set; otherwise, an interrupt is not generated. 0 r/w pllfim 0 63 october 01, 2007 preliminary lm3s600 microcontroller
register 6: masked interrupt status and clear (misc), offset 0x058 central location for system control result of ris and imc to generate an interrupt to the controller . all of the bits are r/w1c and this action also clears the corresponding raw interrupt bit in the ris register (see page 61 ). masked interrupt status and clear (misc) base 0x400f .e000 of fset 0x058 t ype r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved bormis ldomis mofmis iofmis clmis plllmis reserved ro r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:7 pll lock masked interrupt status this bit is set when the pll t ready timer asserts. the interrupt is cleared by writing a 1 to this bit. 0 r/w1c plllmis 6 current limit masked interrupt status this bit is set if the ldo s cle output asserts. the interrupt is cleared by writing a 1 to this bit. 0 r/w1c clmis 5 internal oscillator fault masked interrupt status this bit is set if an internal oscillator fault is detected. the interrupt is cleared by writing a 1 to this bit. 0 r/w1c iofmis 4 main oscillator fault masked interrupt status this bit is set if a main oscillator fault is detected. the interrupt is cleared by writing a 1 to this bit. 0 r/w1c mofmis 3 ldo power unregulated masked interrupt status this bit is set if ldo power is unregulated. the interrupt is cleared by writing a 1 to this bit. 0 r/w1c ldomis 2 bor masked interrupt status this bit is the masked interrupt status for any brown-out conditions. if set, a brown-out condition was detected. an interrupt is reported if the borim bit in the imc register is set and the borior bit in the pborctl register is cleared. the interrupt is cleared by writing a 1 to this bit. 0 r/w1c bormis 1 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 0 october 01, 2007 64 preliminary system control
register 7: reset cause (resc), offset 0x05c this field specifies the cause of the reset event to software. the reset value is determined by the cause of the reset. when an external reset is the cause ( ext is set), all other reset bits are cleared. however , if the reset is due to any other cause, the remaining bits are sticky , allowing software to see all causes. reset cause (resc) base 0x400f .e000 of fset 0x05c t ype r/w , reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 ext por bor wdt sw ldo reserved r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro t ype - - - - - - 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:6 ldo reset when set, indicates the ldo circuit has lost regulation and has generated a reset event. - r/w ldo 5 software reset when set, indicates a software reset is the cause of the reset event. - r/w sw 4 w atchdog t imer reset when set, indicates a watchdog reset is the cause of the reset event. - r/w wdt 3 brown-out reset when set, indicates a brown-out reset is the cause of the reset event. - r/w bor 2 power-on reset when set, indicates a power-on reset is the cause of the reset event. - r/w por 1 external reset when set, indicates an external reset ( rst assertion) is the cause of the reset event. - r/w ext 0 65 october 01, 2007 preliminary lm3s600 microcontroller
register 8: run-mode clock configuration (rcc), offset 0x060 this register is defined to provide source control and frequency speed. run-mode clock configuration (rcc) base 0x400f .e000 of fset 0x060 t ype r/w , reset 0x07a0.3ad1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved usesysdiv sysdiv acg reserved ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w ro ro ro ro t ype 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 moscdis ioscdis moscver ioscver oscsrc xt al pll ver byp ass oen pwrdn reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro t ype 1 0 0 0 0 0 1 1 0 1 0 1 1 1 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:28 auto clock gating this bit specifies whether the system uses the sleep-mode clock gating control (scgcn) registers and deep-sleep-mode clock gating control (dcgcn) registers if the controller enters a sleep or deep-sleep mode (respectively). if set, the scgcn or dcgcn registers are used to control the clocks distributed to the peripherals when the controller is in a sleep mode. otherwise, the run-mode clock gating control (rcgcn) registers are used when the controller enters a sleep mode. the rcgcn registers are always used to control the clocks in run mode. this allows peripherals to consume less power when the controller is in a sleep mode and the peripheral is unused. 0 r/w acg 27 october 01, 2007 66 preliminary system control
description reset t ype name bit/field system clock divisor specifies which divisor is used to generate the system clock from the pll output. the pll vco frequency is 200 mhz. frequency (byp ass=0) divisor (byp ass=1) v alue reserved reserved 0x0 reserved /2 0x1 reserved /3 0x2 50 mhz /4 0x3 40 mhz /5 0x4 33.33 mhz /6 0x5 28.57 mhz /7 0x6 25 mhz /8 0x7 22.22 mhz /9 0x8 20 mhz /10 0x9 18.18 mhz /1 1 0xa 16.67 mhz /12 0xb 15.38 mhz /13 0xc 14.29 mhz /14 0xd 13.33 mhz /15 0xe 12.5 mhz (default) /16 0xf when reading the run-mode clock configuration (rcc) register (see page 66 ), the sysdiv value is minsysdiv if a lower divider was requested and the pll is being used. this lower value is allowed to divide a non-pll source. 0xf r/w sysdiv 26:23 enable system clock divider use the system clock divider as the source for the system clock. the system clock divider is forced to be used when the pll is selected as the source. 0 r/w usesysdiv 22 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 21:14 pll power down this bit connects to the pll pwrdn input. the reset value of 1 powers down the pll. see t able 6-2 on page 69 for pll mode control. 1 r/w pwrdn 13 pll output enable this bit specifies whether the pll output driver is enabled. if cleared, the driver transmits the pll clock to the output. otherwise, the pll clock does not oscillate outside the pll module. note: both pwrdn and oen must be cleared to run the pll. 1 r/w oen 12 67 october 01, 2007 preliminary lm3s600 microcontroller
description reset t ype name bit/field pll bypass chooses whether the system clock is derived from the pll output or the osc source. if set, the clock that drives the system is the osc source. otherwise, the clock that drives the system is the pll output clock divided by the system divider . 1 r/w byp ass 1 1 pll v erification this bit controls the pll verification timer function. if set, the verification timer is enabled and an interrupt is generated if the pll becomes inoperative. otherwise, the verification timer is not enabled. 0 r/w pll ver 10 crystal v alue this field specifies the crystal value attached to the main oscillator . the encoding for this field is provided below . crystal frequency (mhz) using the pll crystal frequency (mhz) not using the pll v alue reserved 1.000 0x0 reserved 1.8432 0x1 reserved 2.000 0x2 reserved 2.4576 0x3 3.579545 mhz 0x4 3.6864 mhz 0x5 4 mhz 0x6 4.096 mhz 0x7 4.9152 mhz 0x8 5 mhz 0x9 5.12 mhz 0xa 6 mhz (reset value) 0xb 6.144 mhz 0xc 7.3728 mhz 0xd 8 mhz 0xe 8.192 mhz 0xf 0xb r/w xt al 9:6 oscillator source picks among the four input sources for the osc. the values are: input source v alue main oscillator (default) 0x0 internal oscillator (default) 0x1 internal oscillator / 4 (this is necessary if used as input to pll) 0x2 reserved 0x3 0x0 r/w oscsrc 5:4 internal oscillator v erification t imer this bit controls the internal oscillator verification timer function. if set, the verification timer is enabled and an interrupt is generated if the timer becomes inoperative. otherwise, the verification timer is not enabled. 0 r/w ioscver 3 october 01, 2007 68 preliminary system control
description reset t ype name bit/field main oscillator v erification t imer this bit controls the main oscillator verification timer function. if set, the verification timer is enabled and an interrupt is generated if the timer becomes inoperative. otherwise, the verification timer is not enabled. 0 r/w moscver 2 internal oscillator disable 0: internal oscillator (iosc) is enabled. 1: internal oscillator is disabled. 0 r/w ioscdis 1 main oscillator disable 0: main oscillator is enabled. 1: main oscillator is disabled (default). 1 r/w moscdis 0 t able 6-2. pll mode control mode oen pwrdn power down x 1 normal 0 0 69 october 01, 2007 preliminary lm3s600 microcontroller
register 9: xt al to pll t ranslation (pllcfg), offset 0x064 this register provides a means of translating external crystal frequencies into the appropriate pll settings. this register is initialized during the reset sequence and updated anytime that the xtal field changes in the run-mode clock configuration (rcc) register (see page 66 ). the pll frequency is calculated using the pllcfg field values, as follows: pllfreq = oscfreq * (f + 2) / (r + 2) xt al to pll t ranslation (pllcfg) base 0x400f .e000 of fset 0x064 t ype ro, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 r f od ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype - - - - - - - - - - - - - - - - reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:16 pll od v alue this field specifies the value supplied to the pll s od input. description v alue divide by 1 0x0 divide by 2 0x1 divide by 4 0x2 reserved 0x3 - ro od 15:14 pll f v alue this field specifies the value supplied to the pll s f input. - ro f 13:5 pll r v alue this field specifies the value supplied to the pll s r input. - ro r 4:0 october 01, 2007 70 preliminary system control
register 10: deep sleep clock configuration (dslpclkcfg), offset 0x144 this register is used to automatically switch from the main oscillator to the internal oscillator when entering deep-sleep mode. the system clock source is the main oscillator by default. when this register is set, the internal oscillator is powered up and the main oscillator is powered down. when the deep-sleep exit event occurs, hardware brings the system clock back to the source and frequency it had at the onset of deep-sleep mode. deep sleep clock configuration (dslpclkcfg) base 0x400f .e000 of fset 0x144 t ype r/w , reset 0x0780.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 iosc reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:1 iosc clock source when set, forces iosc to be clock source during deep-sleep (overrides dsoscsrc field if set) 0 r/w iosc 0 71 october 01, 2007 preliminary lm3s600 microcontroller
register 1 1: clock v erification clear (clkvclr), offset 0x150 this register is provided as a means of clearing the clock verification circuits by software. since the clock verification circuits force a known good clock to control the process, the controller is allowed the opportunity to solve the problem and clear the verification fault. this register clears all clock verification faults. t o clear a clock verification fault, the verclr bit must be set and then cleared by software. this bit is not self-clearing. clock v erification clear (clkvclr) base 0x400f .e000 of fset 0x150 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 verclr reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:1 clock v erification clear clears clock verification faults. 0 r/w verclr 0 october 01, 2007 72 preliminary system control
register 12: allow unregulated ldo to reset the part (ldoarst), offset 0x160 this register is provided as a means of allowing the ldo to reset the part if the voltage goes unregulated. use this register to choose whether to automatically reset the part if the ldo goes unregulated, based on the design tolerance for ldo fluctuation. allow unregulated ldo to reset the part (ldoarst) base 0x400f .e000 of fset 0x160 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 ldoarst reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:1 ldo reset when set, allows unregulated ldo output to reset the part. 0 r/w ldoarst 0 73 october 01, 2007 preliminary lm3s600 microcontroller
register 13: device identification 1 (did1), offset 0x004 this register identifies the device family , part number , temperature range, and package type. device identification 1 (did1) base 0x400f .e000 of fset 0x004 t ype ro, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 p ar tno f am ver ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 qual rohs pkg temp reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype - - 1 1 0 1 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field did1 v ersion this field defines the did1 register format version. the version number is numeric. the value of the ver field is encoded as follows (all other encodings are reserved): description v alue initial did1 register format definition, indicating a stellaris lm3snnn device. 0x0 0x0 ro ver 31:28 family this field provides the family identification of the device within the luminary micro product portfolio. the value is encoded as follows (all other encodings are reserved): description v alue stellaris family of microcontollers, that is, all devices with external part numbers starting with lm3s. 0x0 0x0 ro f am 27:24 part number this field provides the part number of the device within the family . the value is encoded as follows (all other encodings are reserved): description v alue lm3s600 0x2a 0x2a ro p ar tno 23:16 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:8 october 01, 2007 74 preliminary system control
description reset t ype name bit/field t emperature range this field specifies the temperature rating of the device. the value is encoded as follows (all other encodings are reserved): description v alue industrial temperature range (-40c to 85c) 0x1 0x1 ro temp 7:5 package t ype this field specifies the package type. the value is encoded as follows (all other encodings are reserved): description v alue 48-pin lqfp package 0x1 0x1 ro pkg 4:3 rohs-compliance this bit specifies whether the device is rohs-compliant. a 1 indicates the part is rohs-compliant. 1 ro rohs 2 qualification status this field specifies the qualification status of the device. the value is encoded as follows (all other encodings are reserved): description v alue engineering sample (unqualified) 0x0 pilot production (unqualified) 0x1 fully qualified 0x2 - ro qual 1:0 75 october 01, 2007 preliminary lm3s600 microcontroller
register 14: device capabilities 0 (dc0), offset 0x008 this register is predefined by the part and can be used to verify features. device capabilities 0 (dc0) base 0x400f .e000 of fset 0x008 t ype ro, reset 0x001f .000f 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 sramsz ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 flashsz ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field sram size indicates the size of the on-chip sram memory . description v alue 8 kb of sram 0x001f 0x001f ro sramsz 31:16 flash size indicates the size of the on-chip flash memory . description v alue 32 kb of flash 0x000f 0x000f ro flashsz 15:0 october 01, 2007 76 preliminary system control
register 15: device capabilities 1 (dc1), offset 0x010 this register provides a list of features available in the system. the stellaris family uses this register format to indicate the availability of the following family features in the specific device: pwm, adc, w atchdog timer , and debug capabilities. this register also indicates the maximum clock frequency and maximum adc sample rate. the format of this register is consistent with the rcgc0 , scgc0 , and dcgc0 clock control registers and the srcr0 software reset control register . device capabilities 1 (dc1) base 0x400f .e000 of fset 0x010 t ype ro, reset 0x0000.309f 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 jt ag swd swo wdt pll reserved mpu reserved minsysdiv ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 1 1 1 1 0 0 1 0 0 0 0 1 1 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:16 system clock divider minimum 4-bit divider value for system clock. the reset value is hardware-dependent. see the rcc register for how to change the system clock divisor using the sysdiv bit. description v alue specifies a 50-mhz cpu clock with a pll divider of 4. 0x3 0x3 ro minsysdiv 15:12 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 1 1:8 mpu present when set, indicates that the cortex-m3 memory protection unit (mpu) module is present. see the arm cortex-m3 t echnical reference manual for details on the mpu. 1 ro mpu 7 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 6:5 pll present when set, indicates that the on-chip phase locked loop (pll) is present. 1 ro pll 4 w atchdog t imer present when set, indicates that a watchdog timer is present. 1 ro wdt 3 77 october 01, 2007 preliminary lm3s600 microcontroller
description reset t ype name bit/field swo t race port present when set, indicates that the serial wire output (swo) trace port is present. 1 ro swo 2 swd present when set, indicates that the serial wire debugger (swd) is present. 1 ro swd 1 jt ag present when set, indicates that the jt ag debugger interface is present. 1 ro jt ag 0 october 01, 2007 78 preliminary system control
register 16: device capabilities 2 (dc2), offset 0x014 this register provides a list of features available in the system. the stellaris family uses this register format to indicate the availability of the following family features in the specific device: analog comparators, general-purpose t imers, i2cs, qeis, ssis, and uar t s. the format of this register is consistent with the rcgc1 , scgc1 , and dcgc1 clock control registers and the srcr1 software reset control register . device capabilities 2 (dc2) base 0x400f .e000 of fset 0x014 t ype ro, reset 0x0707.1013 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 timer0 timer1 timer2 reserved comp0 comp1 comp2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 uar t0 uar t1 reserved ssi0 reserved i2c0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:27 analog comparator 2 present when set, indicates that analog comparator 2 is present. 1 ro comp2 26 analog comparator 1 present when set, indicates that analog comparator 1 is present. 1 ro comp1 25 analog comparator 0 present when set, indicates that analog comparator 0 is present. 1 ro comp0 24 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:19 t imer 2 present when set, indicates that general-purpose t imer module 2 is present. 1 ro timer2 18 t imer 1 present when set, indicates that general-purpose t imer module 1 is present. 1 ro timer1 17 t imer 0 present when set, indicates that general-purpose t imer module 0 is present. 1 ro timer0 16 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:13 i2c module 0 present when set, indicates that i2c module 0 is present. 1 ro i2c0 12 79 october 01, 2007 preliminary lm3s600 microcontroller
description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 1 1:5 ssi0 present when set, indicates that ssi module 0 is present. 1 ro ssi0 4 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3:2 uar t1 present when set, indicates that uar t module 1 is present. 1 ro uar t1 1 uar t0 present when set, indicates that uar t module 0 is present. 1 ro uar t0 0 october 01, 2007 80 preliminary system control
register 17: device capabilities 3 (dc3), offset 0x018 this register provides a list of features available in the system. the stellaris family uses this register format to indicate the availability of the following family features in the specific device: analog comparator i/os, ccp i/os, adc i/os, and pwm i/os. device capabilities 3 (dc3) base 0x400f .e000 of fset 0x018 t ype ro, reset 0x3f00.7fc0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ccp0 ccp1 ccp2 ccp3 ccp4 ccp5 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved c0minus c0plus c0o c1minus c1plus c1o c2minus c2plus c2o reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:30 ccp5 pin present when set, indicates that capture/compare/pwm pin 5 is present. 1 ro ccp5 29 ccp4 pin present when set, indicates that capture/compare/pwm pin 4 is present. 1 ro ccp4 28 ccp3 pin present when set, indicates that capture/compare/pwm pin 3 is present. 1 ro ccp3 27 ccp2 pin present when set, indicates that capture/compare/pwm pin 2 is present. 1 ro ccp2 26 ccp1 pin present when set, indicates that capture/compare/pwm pin 1 is present. 1 ro ccp1 25 ccp0 pin present when set, indicates that capture/compare/pwm pin 0 is present. 1 ro ccp0 24 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:15 c2o pin present when set, indicates that the analog comparator 2 output pin is present. 1 ro c2o 14 c2+ pin present when set, indicates that the analog comparator 2 (+) input pin is present. 1 ro c2plus 13 81 october 01, 2007 preliminary lm3s600 microcontroller
description reset t ype name bit/field c2- pin present when set, indicates that the analog comparator 2 (-) input pin is present. 1 ro c2minus 12 c1o pin present when set, indicates that the analog comparator 1 output pin is present. 1 ro c1o 1 1 c1+ pin present when set, indicates that the analog comparator 1 (+) input pin is present. 1 ro c1plus 10 c1- pin present when set, indicates that the analog comparator 1 (-) input pin is present. 1 ro c1minus 9 c0o pin present when set, indicates that the analog comparator 0 output pin is present. 1 ro c0o 8 c0+ pin present when set, indicates that the analog comparator 0 (+) input pin is present. 1 ro c0plus 7 c0- pin present when set, indicates that the analog comparator 0 (-) input pin is present. 1 ro c0minus 6 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 5:0 october 01, 2007 82 preliminary system control
register 18: device capabilities 4 (dc4), offset 0x01c this register provides a list of features available in the system. the stellaris family uses this register format to indicate the availability of gpios in the specific device. the format of this register is consistent with the rcgc2 , scgc2 , and dcgc2 clock control registers and the srcr2 software reset control register . device capabilities 4 (dc4) base 0x400f .e000 of fset 0x01c t ype ro, reset 0x0000.001f 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 gpioa gpiob gpioc gpiod gpioe reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:5 gpio port e present when set, indicates that gpio port e is present. 1 ro gpioe 4 gpio port d present when set, indicates that gpio port d is present. 1 ro gpiod 3 gpio port c present when set, indicates that gpio port c is present. 1 ro gpioc 2 gpio port b present when set, indicates that gpio port b is present. 1 ro gpiob 1 gpio port a present when set, indicates that gpio port a is present. 1 ro gpioa 0 83 october 01, 2007 preliminary lm3s600 microcontroller
register 19: run mode clock gating control register 0 (rcgc0), offset 0x100 this register controls the clock gating logic. each bit controls a clock enable for a given interface, function, or unit. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled (saving power). if the unit is unclocked, reads or writes to the unit will generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or units to control. this is to assure reasonable code compatibility with other family and future parts. rcgc0 is the clock configuration register for running operation, scgc0 for sleep operation, and dcgc0 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. run mode clock gating control register 0 (rcgc0) base 0x400f .e000 of fset 0x100 t ype r/w , reset 0x00000040 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved wdt reserved ro ro ro r/w ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:4 wdt clock gating control this bit controls the clock gating for the wdt module. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, a read or write to the unit generates a bus fault. 0 r/w wdt 3 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 2:0 october 01, 2007 84 preliminary system control
register 20: sleep mode clock gating control register 0 (scgc0), offset 0x1 10 this register controls the clock gating logic. each bit controls a clock enable for a given interface, function, or unit. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled (saving power). if the unit is unclocked, reads or writes to the unit will generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or units to control. this is to assure reasonable code compatibility with other family and future parts. rcgc0 is the clock configuration register for running operation, scgc0 for sleep operation, and dcgc0 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. sleep mode clock gating control register 0 (scgc0) base 0x400f .e000 of fset 0x1 10 t ype r/w , reset 0x00000040 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved wdt reserved ro ro ro r/w ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:4 wdt clock gating control this bit controls the clock gating for the wdt module. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, a read or write to the unit generates a bus fault. 0 r/w wdt 3 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 2:0 85 october 01, 2007 preliminary lm3s600 microcontroller
register 21: deep sleep mode clock gating control register 0 (dcgc0), offset 0x120 this register controls the clock gating logic. each bit controls a clock enable for a given interface, function, or unit. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled (saving power). if the unit is unclocked, reads or writes to the unit will generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or units to control. this is to assure reasonable code compatibility with other family and future parts. rcgc0 is the clock configuration register for running operation, scgc0 for sleep operation, and dcgc0 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. deep sleep mode clock gating control register 0 (dcgc0) base 0x400f .e000 of fset 0x120 t ype r/w , reset 0x00000040 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved wdt reserved ro ro ro r/w ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:4 wdt clock gating control this bit controls the clock gating for the wdt module. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, a read or write to the unit generates a bus fault. 0 r/w wdt 3 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 2:0 october 01, 2007 86 preliminary system control
register 22: run mode clock gating control register 1 (rcgc1), offset 0x104 this register controls the clock gating logic. each bit controls a clock enable for a given interface, function, or unit. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled (saving power). if the unit is unclocked, reads or writes to the unit will generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or units to control. this is to assure reasonable code compatibility with other family and future parts. rcgc1 is the clock configuration register for running operation, scgc1 for sleep operation, and dcgc1 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. run mode clock gating control register 1 (rcgc1) base 0x400f .e000 of fset 0x104 t ype r/w , reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 timer0 timer1 timer2 reserved comp0 comp1 comp2 reserved r/w r/w r/w ro ro ro ro ro r/w r/w r/w ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 uar t0 uar t1 reserved ssi0 reserved i2c0 reserved r/w r/w ro ro r/w ro ro ro ro ro ro ro r/w ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:27 analog comparator 2 clock gating this bit controls the clock gating for analog comparator 2. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w comp2 26 analog comparator 1 clock gating this bit controls the clock gating for analog comparator 1. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w comp1 25 analog comparator 0 clock gating this bit controls the clock gating for analog comparator 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w comp0 24 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:19 87 october 01, 2007 preliminary lm3s600 microcontroller
description reset t ype name bit/field t imer 2 clock gating control this bit controls the clock gating for general-purpose t imer module 2. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w timer2 18 t imer 1 clock gating control this bit controls the clock gating for general-purpose t imer module 1. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w timer1 17 t imer 0 clock gating control this bit controls the clock gating for general-purpose t imer module 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w timer0 16 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:13 i2c0 clock gating control this bit controls the clock gating for i2c module 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w i2c0 12 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 1 1:5 ssi0 clock gating control this bit controls the clock gating for ssi module 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w ssi0 4 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3:2 uar t1 clock gating control this bit controls the clock gating for uar t module 1. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w uar t1 1 uar t0 clock gating control this bit controls the clock gating for uar t module 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w uar t0 0 october 01, 2007 88 preliminary system control
register 23: sleep mode clock gating control register 1 (scgc1), offset 0x1 14 this register controls the clock gating logic. each bit controls a clock enable for a given interface, function, or unit. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled (saving power). if the unit is unclocked, reads or writes to the unit will generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or units to control. this is to assure reasonable code compatibility with other family and future parts. rcgc1 is the clock configuration register for running operation, scgc1 for sleep operation, and dcgc1 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. sleep mode clock gating control register 1 (scgc1) base 0x400f .e000 of fset 0x1 14 t ype r/w , reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 timer0 timer1 timer2 reserved comp0 comp1 comp2 reserved r/w r/w r/w ro ro ro ro ro r/w r/w r/w ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 uar t0 uar t1 reserved ssi0 reserved i2c0 reserved r/w r/w ro ro r/w ro ro ro ro ro ro ro r/w ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:27 analog comparator 2 clock gating this bit controls the clock gating for analog comparator 2. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w comp2 26 analog comparator 1 clock gating this bit controls the clock gating for analog comparator 1. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w comp1 25 analog comparator 0 clock gating this bit controls the clock gating for analog comparator 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w comp0 24 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:19 89 october 01, 2007 preliminary lm3s600 microcontroller
description reset t ype name bit/field t imer 2 clock gating control this bit controls the clock gating for general-purpose t imer module 2. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w timer2 18 t imer 1 clock gating control this bit controls the clock gating for general-purpose t imer module 1. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w timer1 17 t imer 0 clock gating control this bit controls the clock gating for general-purpose t imer module 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w timer0 16 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:13 i2c0 clock gating control this bit controls the clock gating for i2c module 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w i2c0 12 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 1 1:5 ssi0 clock gating control this bit controls the clock gating for ssi module 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w ssi0 4 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3:2 uar t1 clock gating control this bit controls the clock gating for uar t module 1. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w uar t1 1 uar t0 clock gating control this bit controls the clock gating for uar t module 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w uar t0 0 october 01, 2007 90 preliminary system control
register 24: deep sleep mode clock gating control register 1 (dcgc1), offset 0x124 this register controls the clock gating logic. each bit controls a clock enable for a given interface, function, or unit. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled (saving power). if the unit is unclocked, reads or writes to the unit will generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or units to control. this is to assure reasonable code compatibility with other family and future parts. rcgc1 is the clock configuration register for running operation, scgc1 for sleep operation, and dcgc1 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. deep sleep mode clock gating control register 1 (dcgc1) base 0x400f .e000 of fset 0x124 t ype r/w , reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 timer0 timer1 timer2 reserved comp0 comp1 comp2 reserved r/w r/w r/w ro ro ro ro ro r/w r/w r/w ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 uar t0 uar t1 reserved ssi0 reserved i2c0 reserved r/w r/w ro ro r/w ro ro ro ro ro ro ro r/w ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:27 analog comparator 2 clock gating this bit controls the clock gating for analog comparator 2. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w comp2 26 analog comparator 1 clock gating this bit controls the clock gating for analog comparator 1. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w comp1 25 analog comparator 0 clock gating this bit controls the clock gating for analog comparator 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w comp0 24 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:19 91 october 01, 2007 preliminary lm3s600 microcontroller
description reset t ype name bit/field t imer 2 clock gating control this bit controls the clock gating for general-purpose t imer module 2. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w timer2 18 t imer 1 clock gating control this bit controls the clock gating for general-purpose t imer module 1. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w timer1 17 t imer 0 clock gating control this bit controls the clock gating for general-purpose t imer module 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w timer0 16 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:13 i2c0 clock gating control this bit controls the clock gating for i2c module 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w i2c0 12 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 1 1:5 ssi0 clock gating control this bit controls the clock gating for ssi module 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w ssi0 4 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3:2 uar t1 clock gating control this bit controls the clock gating for uar t module 1. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w uar t1 1 uar t0 clock gating control this bit controls the clock gating for uar t module 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w uar t0 0 october 01, 2007 92 preliminary system control
register 25: run mode clock gating control register 2 (rcgc2), offset 0x108 this register controls the clock gating logic. each bit controls a clock enable for a given interface, function, or unit. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled (saving power). if the unit is unclocked, reads or writes to the unit will generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or units to control. this is to assure reasonable code compatibility with other family and future parts. rcgc2 is the clock configuration register for running operation, scgc2 for sleep operation, and dcgc2 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. run mode clock gating control register 2 (rcgc2) base 0x400f .e000 of fset 0x108 t ype r/w , reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 gpioa gpiob gpioc gpiod gpioe reserved r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:5 port e clock gating control this bit controls the clock gating for port e. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpioe 4 port d clock gating control this bit controls the clock gating for port d. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpiod 3 port c clock gating control this bit controls the clock gating for port c. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpioc 2 port b clock gating control this bit controls the clock gating for port b. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpiob 1 93 october 01, 2007 preliminary lm3s600 microcontroller
description reset t ype name bit/field port a clock gating control this bit controls the clock gating for port a. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpioa 0 october 01, 2007 94 preliminary system control
register 26: sleep mode clock gating control register 2 (scgc2), offset 0x1 18 this register controls the clock gating logic. each bit controls a clock enable for a given interface, function, or unit. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled (saving power). if the unit is unclocked, reads or writes to the unit will generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or units to control. this is to assure reasonable code compatibility with other family and future parts. rcgc2 is the clock configuration register for running operation, scgc2 for sleep operation, and dcgc2 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. sleep mode clock gating control register 2 (scgc2) base 0x400f .e000 of fset 0x1 18 t ype r/w , reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 gpioa gpiob gpioc gpiod gpioe reserved r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:5 port e clock gating control this bit controls the clock gating for port e. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpioe 4 port d clock gating control this bit controls the clock gating for port d. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpiod 3 port c clock gating control this bit controls the clock gating for port c. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpioc 2 port b clock gating control this bit controls the clock gating for port b. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpiob 1 95 october 01, 2007 preliminary lm3s600 microcontroller
description reset t ype name bit/field port a clock gating control this bit controls the clock gating for port a. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpioa 0 october 01, 2007 96 preliminary system control
register 27: deep sleep mode clock gating control register 2 (dcgc2), offset 0x128 this register controls the clock gating logic. each bit controls a clock enable for a given interface, function, or unit. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled (saving power). if the unit is unclocked, reads or writes to the unit will generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or units to control. this is to assure reasonable code compatibility with other family and future parts. rcgc2 is the clock configuration register for running operation, scgc2 for sleep operation, and dcgc2 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. deep sleep mode clock gating control register 2 (dcgc2) base 0x400f .e000 of fset 0x128 t ype r/w , reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 gpioa gpiob gpioc gpiod gpioe reserved r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:5 port e clock gating control this bit controls the clock gating for port e. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpioe 4 port d clock gating control this bit controls the clock gating for port d. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpiod 3 port c clock gating control this bit controls the clock gating for port c. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpioc 2 port b clock gating control this bit controls the clock gating for port b. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpiob 1 97 october 01, 2007 preliminary lm3s600 microcontroller
description reset t ype name bit/field port a clock gating control this bit controls the clock gating for port a. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpioa 0 october 01, 2007 98 preliminary system control
register 28: software reset control 0 (srcr0), offset 0x040 w rites to this register are masked by the bits in the device capabilities 1 (dc1) register . software reset control 0 (srcr0) base 0x400f .e000 of fset 0x040 t ype r/w , reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved wdt reserved ro ro ro r/w ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:4 wdt reset control reset control for w atchdog unit. 0 r/w wdt 3 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 2:0 99 october 01, 2007 preliminary lm3s600 microcontroller
register 29: software reset control 1 (srcr1), offset 0x044 w rites to this register are masked by the bits in the device capabilities 2 (dc2) register . software reset control 1 (srcr1) base 0x400f .e000 of fset 0x044 t ype r/w , reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 timer0 timer1 timer2 reserved comp0 comp1 comp2 reserved r/w r/w r/w ro ro ro ro ro r/w r/w r/w ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 uar t0 uar t1 reserved ssi0 reserved i2c0 reserved r/w r/w ro ro r/w ro ro ro ro ro ro ro r/w ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:27 analog comp 2 reset control reset control for analog comparator 2. 0 r/w comp2 26 analog comp 1 reset control reset control for analog comparator 1. 0 r/w comp1 25 analog comp 0 reset control reset control for analog comparator 0. 0 r/w comp0 24 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:19 t imer 2 reset control reset control for general-purpose t imer module 2. 0 r/w timer2 18 t imer 1 reset control reset control for general-purpose t imer module 1. 0 r/w timer1 17 t imer 0 reset control reset control for general-purpose t imer module 0. 0 r/w timer0 16 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:13 i2c0 reset control reset control for i2c unit 0. 0 r/w i2c0 12 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 1 1:5 october 01, 2007 100 preliminary system control
description reset t ype name bit/field ssi0 reset control reset control for ssi unit 0. 0 r/w ssi0 4 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3:2 uar t1 reset control reset control for uar t unit 1. 0 r/w uar t1 1 uar t0 reset control reset control for uar t unit 0. 0 r/w uar t0 0 101 october 01, 2007 preliminary lm3s600 microcontroller
register 30: software reset control 2 (srcr2), offset 0x048 w rites to this register are masked by the bits in the device capabilities 4 (dc4) register . software reset control 2 (srcr2) base 0x400f .e000 of fset 0x048 t ype r/w , reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 gpioa gpiob gpioc gpiod gpioe reserved r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:5 port e reset control reset control for gpio port e. 0 r/w gpioe 4 port d reset control reset control for gpio port d. 0 r/w gpiod 3 port c reset control reset control for gpio port c. 0 r/w gpioc 2 port b reset control reset control for gpio port b. 0 r/w gpiob 1 port a reset control reset control for gpio port a. 0 r/w gpioa 0 october 01, 2007 102 preliminary system control
7 internal memory the lm3s600 microcontroller comes with 8 kb of bit-banded sram and 32 kb of flash memory . the flash controller provides a user-friendly interface, making flash programming a simple task. flash protection can be applied to the flash memory on a 2-kb block basis. 7.1 block diagram figure 7-1. flash block diagram 7.2 functional description this section describes the functionality of both the flash and sram memories. 7.2.1 sram memory the internal sram of the stellaris ? devices is located at address 0x2000.0000 of the device memory map. t o reduce the number of time consuming read-modify-write (rmw) operations, arm has introduced bit-banding technology in the cortex-m3 processor . with a bit-band-enabled processor , certain regions in the memory map (sram and peripheral space) can use address aliases to access individual bits in a single, atomic operation. the bit-band alias is calculated by using the formula: 103 october 01, 2007 preliminary lm3s600 microcontroller flash control fma fcmisc fcim fcris fmc fmd flash t iming usecrl flash protection fmpre fmppe flash array sram array bridge cortex-m3 icode dcode system bus apb
bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4) for example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as: 0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000c with the alias address calculated, an instruction performing a read/write to address 0x2202.000c allows direct access to only bit 3 of the byte at address 0x2000.1000. for details about bit-banding, please refer to chapter 4, memory map in the arm? cortex?-m3 t echnical reference manual . 7.2.2 flash memory the flash is organized as a set of 1-kb blocks that can be individually erased. erasing a block causes the entire contents of the block to be reset to all 1s. an individual 32-bit word can be programmed to change bits that are currently 1 to a 0. these blocks are paired into a set of 2-kb blocks that can be individually protected. the protection allows blocks to be marked as read-only or execute-only , providing dif ferent levels of code protection. read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger . see also serial flash loader on page 360 for a preprogrammed flash-resident utility used to download code to the flash memory of a device without the use of a debug interface. 7.2.2.1 flash memory t iming the timing for the flash is automatically handled by the flash controller . however , in order to do so, it must know the clock rate of the system in order to time its internal signals properly . the number of clock cycles per microsecond must be provided to the flash controller for it to accomplish this timing. it is software's responsibility to keep the flash controller updated with this information via the usec reload (usecrl) register . on reset, the usecrl register is loaded with a value that configures the flash timing so that it works with the maximum clock rate of the part. if software changes the system operating frequency , the new operating frequency minus 1 (in mhz) must be loaded into usecrl before any flash modifications are attempted. for example, if the device is operating at a speed of 20 mhz, a value of 0x13 (20-1) must be written to the usecrl register . 7.2.2.2 flash memory protection the user is provided two forms of flash protection per 2-kb flash blocks in two 32-bit wide registers.the protection policy for each form is controlled by individual bits (per policy per block) in the fmppen and fmpren registers. flash memory protection program enable (fmppen) : if set, the block may be programmed (written) or erased. if cleared, the block may not be changed. flash memory protection read enable (fmpren) : if set, the block may be executed or read by software or debuggers. if cleared, the block may only be executed. the contents of the memory block are prohibited from being accessed as data and traversing the dcode bus. the policies may be combined as shown in t able 7-1 on page 105 . october 01, 2007 104 preliminary internal memory
t able 7-1. flash protection policy combinations protection fmpren fmppen execute-only protection. the block may only be executed and may not be written or erased. this mode is used to protect code. 0 0 the block may be written, erased or executed, but not read. this combination is unlikely to be used. 0 1 read-only protection. the block may be read or executed but may not be written or erased. this mode is used to lock the block from further modification while allowing any read or execute access. 1 0 no protection. the block may be written, erased, executed or read. 1 1 an access that attempts to program or erase a pe-protected block is prohibited. a controller interrupt may be optionally generated (by setting the amask bit in the fim register) to alert software developers of poorly behaving software during the development and debug phases. an access that attempts to read an re-protected block is prohibited. such accesses return data filled with all 0s. a controller interrupt may be optionally generated to alert software developers of poorly behaving software during the development and debug phases. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this implements a policy of open access and programmability . the register bits may be changed by writing the specific register bit. the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. 7.2.2.3 flash protection by disabling debug access flash memory may also be protected by permanently disabling access to the debug access port (dap) through the jt ag and swd interfaces. this is accomplished by clearing the dbg field of the fmpre register . flash memory protection read enable (dbg field): if set to 0x2, access to the dap is enabled through the jt ag and swd interfaces. if clear , access to the dap is disabled. the dbg field programming becomes permanent, and irreversible, after a commit sequence is performed. in the initial state, provided from the factory , access is enabled in order to facilitate code development and debug. access to the dap may be disabled at the end of the manufacturing flow , once all tests have passed and software loaded. this change will not take ef fect until the next power-up of the device. note that it is recommended that disabling access to the dap be combined with a mechanism for providing end-user installable updates (if necessary) such as the stellaris boot loader . important: once the dbg field is cleared and committed, this field can never be restored to the factory-programmed valuewhich means jt ag/swd interface to the debug module can never be re-enabled. this sequence does not disable the jt ag controller , it only disables the access of the dap through the jt ag or swd interfaces. the jt ag interface remains functional and access to the t est access port remains enabled, allowing the user to execute the ieee jt ag-defined instructions (for example, to perform boundary scan operations). if the user will also be using the fmpre bits to protect flash memory from being read as data (to mark sets of 2 kb blocks of flash memory as execute-only), these one-time-programmable bits should be written at the same time that the debug disable bits are programmed. mechanisms to execute the one-time code sequence to disable all debug access include: selecting the debug disable option in the stellaris boot loader 105 october 01, 2007 preliminary lm3s600 microcontroller
loading the debug disable sequence into sram and running it once from sram after programming the final end application code into flash 7.3 flash memory initialization and configuration this section shows examples for using the flash controller to perform various operations on the contents of the flash memory . 7.3.1 changing flash protection bits as discussed in flash memory protection on page 104 , changes to the protection bits must be committed before they take ef fect. the sequence below is used change and commit a block protection bit in the fmpre or fmppe registers. the sequence to change and commit a bit in software is as follows: 1. the flash memory protection read enable (fmpre) and flash memory protection program enable (fmppe) registers are written, changing the intended bit(s). the action of these changes can be tested by software while in this state. 2. the flash memory address (fma) register (see page 109 ) bit 0 is set to 1 if the fmppe register is to be committed; otherwise, a 0 commits the fmpre register . 3. the flash memory control (fmc) register (see page 111 ) is written with the comt bit set. this initiates a write sequence and commits the changes. there is a special sequence to change and commit the dbg bits in the flash memory protection read enable (fmpre) register . this sequence also sets and commits any changes from 1 to 0 in the block protection bits (for execute-only) in the fmpre register . 1. the f lash memory protection read enable (fmpre) register is written, changing the intended bit(s). the action of these changes can be tested by software while in this state. 2. the flash memory address (fma) register (see p page 109 ) is written with a value of 0x900. 3. the flash memory control (fmc) register (see page 111 ) is written with the comt bit set. this initiates a write sequence and commits the changes. below is an example code sequence to permanently disable the jt ag and swd interface to the debug module using luminary micro's driverlib peripheral driver library: #include "hw_types.h" #include "hw_flash.h" void permanently_disable_jtag_swd(void) { // // clear the dbg field of the fmpre register. note that the value // used in this instance does not affect the state of the blockn // bits, but were the value different, all bits in the fmpre are // affected by this function! // hwreg(flash_fmpre) &= 0x3fffffff; // // the following sequence activates the one-time october 01, 2007 106 preliminary internal memory
// programming of the fmpre register. // hwreg(flash_fma) = 0x900; hwreg(flash_fmc) = (flash_fmc_wrkey | flash_fmc_comt); // // wait until the operation is complete. // while (hwreg(flash_fmc) & flash_fmc_comt) { } } 7.3.2 flash programming the stellaris ? devices provide a user-friendly interface for flash programming. all erase/program operations are handled via three registers: fma , fmd , and fmc . 7.3.2.1 t o program a 32-bit word 1. w rite source data to the fmd register . 2. w rite the target address to the fma register . 3. w rite the flash write key and the write bit (a value of 0xa442.0001) to the fmc register . 4. poll the fmc register until the write bit is cleared. 7.3.2.2 t o perform an erase of a 1-kb page 1. w rite the page address to the fma register . 2. w rite the flash write key and the erase bit (a value of 0xa442.0002) to the fmc register . 3. poll the fmc register until the erase bit is cleared. 7.3.2.3 t o perform a mass erase of the flash 1. w rite the flash write key and the merase bit (a value of 0xa442.0004) to the fmc register . 2. poll the fmc register until the merase bit is cleared. 7.4 register map t able 7-2 on page 108 lists the flash memory and control registers. the of fset listed is a hexadecimal increment to the register's address. the fma , fmd , fmc , fcris , fcim , and fcmisc registers are relative to the flash control base address of 0x400f .d000. the fmpren , fmppen , usecrl , user_dbg , and user_regn registers are relative to the system control base address of 0x400f .e000. 107 october 01, 2007 preliminary lm3s600 microcontroller
t able 7-2. flash register map see page description reset t ype name offset flash control offset 109 flash memory address 0x0000.0000 r/w fma 0x000 110 flash memory data 0x0000.0000 r/w fmd 0x004 111 flash memory control 0x0000.0000 r/w fmc 0x008 113 flash controller raw interrupt status 0x0000.0000 ro fcris 0x00c 114 flash controller interrupt mask 0x0000.0000 r/w fcim 0x010 115 flash controller masked interrupt status and clear 0x0000.0000 r/w1c fcmisc 0x014 system control offset 117 flash memory protection read enable 0x8000.ffff r/w fmpre 0x130 118 flash memory protection program enable 0x0000.ffff r/w fmppe 0x134 116 usec reload 0x31 r/w usecrl 0x140 7.5 flash register descriptions (flash control offset) the remainder of this section lists and describes the flash memory registers, in numerical order by address of fset. registers in this section are relative to the flash control base address of 0x400f .d000. october 01, 2007 108 preliminary internal memory
register 1: flash memory address (fma), offset 0x000 during a write operation, this register contains a 4-byte-aligned address and specifies where the data is written. during erase operations, this register contains a 1 kb-aligned address and specifies which page is erased. note that the alignment requirements must be met by software or the results of the operation are unpredictable. flash memory address (fma) base 0x400f .d000 of fset 0x000 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 offset reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:15 address of fset address of fset in flash where operation is performed. 0x0 r/w offset 14:0 109 october 01, 2007 preliminary lm3s600 microcontroller
register 2: flash memory data (fmd), offset 0x004 this register contains the data to be written during the programming cycle or read during the read cycle. note that the contents of this register are undefined for a read access of an execute-only block. this register is not used during the erase cycles. flash memory data (fmd) base 0x400f .d000 of fset 0x004 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 da t a r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 da t a r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field data v alue data value for write operation. 0x0 r/w da t a 31:0 october 01, 2007 1 10 preliminary internal memory
register 3: flash memory control (fmc), offset 0x008 when this register is written, the flash controller initiates the appropriate access cycle for the location specified by the flash memory address (fma) register (see page 109 ). if the access is a write access, the data contained in the flash memory data (fmd) register (see page 110 ) is written. this is the final register written and initiates the memory operation. there are four control bits in the lower byte of this register that, when set, initiate the memory operation. the most used of these register bits are the erase and write bits. it is a programming error to write multiple control bits and the results of such an operation are unpredictable. flash memory control (fmc) base 0x400f .d000 of fset 0x008 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 wrkey wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 write erase merase comt reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field flash w rite key this field contains a write key , which is used to minimize the incidence of accidental flash writes. the value 0xa442 must be written into this field for a write to occur . w rites to the fmc register without this wrkey value are ignored. a read of this field returns the value 0. 0x0 wo wrkey 31:16 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 15:4 commit register v alue commit (write) of register value to nonvolatile storage. a write of 0 has no ef fect on the state of this bit. if read, the state of the previous commit access is provided. if the previous commit access is complete, a 0 is returned; otherwise, if the commit access is not complete, a 1 is returned. this can take up to 50 s. 0 r/w comt 3 mass erase flash memory if this bit is set, the flash main memory of the device is all erased. a write of 0 has no ef fect on the state of this bit. if read, the state of the previous mass erase access is provided. if the previous mass erase access is complete, a 0 is returned; otherwise, if the previous mass erase access is not complete, a 1 is returned. this can take up to 250 ms. 0 r/w merase 2 1 1 1 october 01, 2007 preliminary lm3s600 microcontroller
description reset t ype name bit/field erase a page of flash memory if this bit is set, the page of flash main memory as specified by the contents of fma is erased. a write of 0 has no ef fect on the state of this bit. if read, the state of the previous erase access is provided. if the previous erase access is complete, a 0 is returned; otherwise, if the previous erase access is not complete, a 1 is returned. this can take up to 25 ms. 0 r/w erase 1 w rite a w ord into flash memory if this bit is set, the data stored in fmd is written into the location as specified by the contents of fma . a write of 0 has no ef fect on the state of this bit. if read, the state of the previous write update is provided. if the previous write access is complete, a 0 is returned; otherwise, if the write access is not complete, a 1 is returned. this can take up to 50 s. 0 r/w write 0 october 01, 2007 1 12 preliminary internal memory
register 4: flash controller raw interrupt status (fcris), offset 0x00c this register indicates that the flash controller has an interrupt condition. an interrupt is only signaled if the corresponding fcim register bit is set. flash controller raw interrupt status (fcris) base 0x400f .d000 of fset 0x00c t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 aris pris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:2 programming raw interrupt status this bit indicates the current state of the programming cycle. if set, the programming cycle completed; if cleared, the programming cycle has not completed. programming cycles are either write or erase actions generated through the flash memory control (fmc) register bits (see page 111 ). 0 ro pris 1 access raw interrupt status this bit indicates if the flash was improperly accessed. if set, the program tried to access the flash counter to the policy as set in the flash memory protection read enable (fmpren) and flash memory protection program enable (fmppen) registers. otherwise, no access has tried to improperly access the flash. 0 ro aris 0 1 13 october 01, 2007 preliminary lm3s600 microcontroller
register 5: flash controller interrupt mask (fcim), offset 0x010 this register controls whether the flash controller generates interrupts to the controller . flash controller interrupt mask (fcim) base 0x400f .d000 of fset 0x010 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 amask pmask reserved r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:2 programming interrupt mask this bit controls the reporting of the programming raw interrupt status to the controller . if set, a programming-generated interrupt is promoted to the controller . otherwise, interrupts are recorded but suppressed from the controller . 0 r/w pmask 1 access interrupt mask this bit controls the reporting of the access raw interrupt status to the controller . if set, an access-generated interrupt is promoted to the controller . otherwise, interrupts are recorded but suppressed from the controller . 0 r/w amask 0 october 01, 2007 1 14 preliminary internal memory
register 6: flash controller masked interrupt status and clear (fcmisc), offset 0x014 this register provides two functions. first, it reports the cause of an interrupt by indicating which interrupt source or sources are signalling the interrupt. second, it serves as the method to clear the interrupt reporting. flash controller masked interrupt status and clear (fcmisc) base 0x400f .d000 of fset 0x014 t ype r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 amisc pmisc reserved r/w1c r/w1c ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:2 programming masked interrupt status and clear this bit indicates whether an interrupt was signaled because a programming cycle completed and was not masked. this bit is cleared by writing a 1. the pris bit in the fcris register (see page 113 ) is also cleared when the pmisc bit is cleared. 0 r/w1c pmisc 1 access masked interrupt status and clear this bit indicates whether an interrupt was signaled because an improper access was attempted and was not masked. this bit is cleared by writing a 1. the aris bit in the fcris register is also cleared when the amisc bit is cleared. 0 r/w1c amisc 0 7.6 flash register descriptions (system control offset) the remainder of this section lists and describes the flash memory registers, in numerical order by address of fset. registers in this section are relative to the system control base address of 0x400f .e000. 1 15 october 01, 2007 preliminary lm3s600 microcontroller
register 7: usec reload (usecrl), offset 0x140 note: of fset is relative to system control base address of 0x400f .e000 this register is provided as a means of creating a 1-s tick divider reload value for the flash controller . the internal flash has specific minimum and maximum requirements on the length of time the high voltage write pulse can be applied. it is required that this register contain the operating frequency (in mhz -1) whenever the flash is being erased or programmed. the user is required to change this value if the clocking conditions are changed for a flash erase/program operation. usec reload (usecrl) base 0x400f .e000 of fset 0x140 t ype r/w , reset 0x31 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 usec reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 microsecond reload v alue mhz -1 of the controller clock when the flash is being erased or programmed. usec should be set to 0x31 (50 mhz) whenever the flash is being erased or programmed. 0x31 r/w usec 7:0 october 01, 2007 1 16 preliminary internal memory
register 8: flash memory protection read enable (fmpre), offset 0x130 note: of fset is relative to system control base address of 0x400fe000. this register stores the read-only protection bits for each 2-kb flash block (see the fmppe registers for the execute-only protection bits). this register is loaded during the power-on reset sequence. the factory settingsare a value of 1 for all implemented banks. this implements a policy of open access and programmability . the register bits may be changed by writing the specific register bit. however , this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. for additional information, see the flash memory protection section. flash memory protection read enable (fmpre) base 0x400f .e000 of fset 0x130 t ype r/w , reset 0x8000.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset t ype name bit/field flash read enable each bit position maps 2 kbytes of flash to be read-enabled. description v alue enables 32 kb of flash. 0x8000ffff 0x8000ffff r/w read_enable 31:0 1 17 october 01, 2007 preliminary lm3s600 microcontroller
register 9: flash memory protection program enable (fmppe), offset 0x134 note: of fset is relative to system control base address of 0x400fe000. this register stores the execute-only protection bits for each 2-kb flash block (see the fmpre registers for the read-only protection bits). this register is loaded during the power-on reset sequence. the factory settings are a value of 1 for all implemented banks. this implements a policy of open access and programmability . the register bits may be changed by writing the specific register bit. however , this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. for additional information, see the flash memory protection section. flash memory protection program enable (fmppe) base 0x400f .e000 of fset 0x134 t ype r/w , reset 0x0000.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset t ype name bit/field flash programming enable each bit position maps 2 kbytes of flash to be write-enabled. description v alue enables 32 kb of flash. 0x0000ffff 0x0000ffff r/w prog_enable 31:0 october 01, 2007 1 18 preliminary internal memory
8 general-purpose input/outputs (gpios) the gpio module is composed of five physical gpio blocks, each corresponding to an individual gpio port (port a, port b, port c, port d, and port e, ). the gpio module is firm-compliant and supports 8-36 programmable input/output pins, depending on the peripherals being used. the gpio module has the following features: programmable control for gpio interrupts C interrupt generation masking C edge-triggered on rising, falling, or both C level-sensitive on high or low values 5-v-tolerant input/outputs bit masking in both read and write operations through address lines programmable control for gpio pad configuration C w eak pull-up or pull-down resistors C 2-ma, 4-ma, and 8-ma pad drive C slew rate control for the 8-ma drive C open drain enables C digital input enables 8.1 functional description important: all gpio pins are inputs by default ( gpiodir =0 and gpioafsel =0), with the exception of the five jt ag pins ( pb7 and pc[3:0] ). the jt ag pins default to their jt ag functionality ( gpioafsel =1). a power-on-reset ( por ) or asserting an external reset ( rst ) puts both groups of pins back to their default state. each gpio port is a separate hardware instantiation of the same physical block (see figure 8-1 on page 120 ). the lm3s600 microcontroller contains five ports and thus five of these physical gpio blocks. 1 19 october 01, 2007 preliminary lm3s600 microcontroller
figure 8-1. gpio port block diagram 8.1.1 data control the data control registers allow software to configure the operational modes of the gpios. the data direction register configures the gpio as an input or an output while the data register either captures incoming data or drives it out to the pads. 8.1.1.1 data direction operation the gpio direction (gpiodir) register (see page 127 ) is used to configure each individual pin as an input or output. when the data direction bit is set to 0, the gpio is configured as an input and the corresponding data register bit will capture and store the value on the gpio port. when the data direction bit is set to 1, the gpio is configured as an output and the corresponding data register bit will be driven out on the gpio port. 8.1.1.2 data register operation t o aid in the ef ficiency of software, the gpio ports allow for the modification of individual bits in the gpio data (gpioda t a) register (see page 126 ) by using bits [9:2] of the address bus as a mask. this allows software drivers to modify individual gpio pins in a single instruction, without af fecting the state of the other pins. this is in contrast to the "typical" method of doing a read-modify-write operation to set or clear an individual gpio pin. t o accommodate this feature, the gpioda t a register covers 256 locations in the memory map. during a write, if the address bit associated with that data bit is set to 1, the value of the gpioda t a register is altered. if it is cleared to 0, it is left unchanged. october 01, 2007 120 preliminary general-purpose input/outputs (gpios) alternate input alternate output alternate output enable interrupt gpio input gpio output gpio output enable pad output pad output enable package i/o pin gpioda t a gpiodir data control gpiois gpioibe gpioiev gpioim gpioris gpiomis gpioicr interrupt control gpiodr2r gpiodr4r gpiodr8r gpioslr gpiopur gpiopdr gpioodr gpioden pad control gpioperiphid0 gpioperiphid1 gpioperiphid2 gpioperiphid3 gpioperiphid4 gpioperiphid5 gpioperiphid6 gpioperiphid7 gpiopcellid0 gpiopcellid1 gpiopcellid2 gpiopcellid3 identification registers gpioafsel mode control mux mux demux digital i /o pad pad input
for example, writing a value of 0xeb to the address gpioda t a + 0x098 would yield as shown in figure 8-2 on page 121 , where u is data unchanged by the write. figure 8-2. gpioda t a w rite example during a read, if the address bit associated with the data bit is set to 1, the value is read. if the address bit associated with the data bit is set to 0, it is read as a zero, regardless of its actual value. for example, reading address gpioda t a + 0x0c4 yields as shown in figure 8-3 on page 121 . figure 8-3. gpioda t a read example 8.1.2 interrupt control the interrupt capabilities of each gpio port are controlled by a set of seven registers. with these registers, it is possible to select the source of the interrupt, its polarity , and the edge properties. when one or more gpio inputs cause an interrupt, a single interrupt output is sent to the interrupt controller for the entire gpio port. for edge-triggered interrupts, software must clear the interrupt to enable any further interrupts. for a level-sensitive interrupt, it is assumed that the external source holds the level constant for the interrupt to be recognized by the controller . three registers are required to define the edge or sense that causes interrupts: gpio interrupt sense (gpiois) register (see page 128 ) gpio interrupt both edges (gpioibe) register (see page 129 ) gpio interrupt event (gpioiev) register (see page 130 ) interrupts are enabled/disabled via the gpio interrupt mask (gpioim) register (see page 131 ). when an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations: the gpio raw interrupt status (gpioris) and gpio masked interrupt status (gpiomis) registers (see page 132 and page 133 ). as the name implies, the gpiomis register only shows interrupt conditions that are allowed to be passed to the controller . the gpioris register indicates that a gpio pin meets the conditions for an interrupt, but has not necessarily been sent to the controller . interrupts are cleared by writing a 1 to the gpio interrupt clear (gpioicr) register (see page 134 ). 121 october 01, 2007 preliminary lm3s600 microcontroller 0 1 0 0 1 1 0 0 1 0 u 1 u u 0 1 u u 9 8 7 6 5 4 3 2 1 0 1 1 1 0 0 1 1 1 7 6 5 4 3 2 1 0 gpioda t a 0xeb 0x098 addr[9:2] 0 1 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 1 1 1 1 1 1 0 7 6 5 4 3 2 1 0 returned v alue gpioda t a 0x0c4 addr[9:2]
when programming the following interrupt control registers, the interrupts should be masked ( gpioim set to 0). w riting any value to an interrupt control register ( gpiois , gpioibe , or gpioiev ) can generate a spurious interrupt if the corresponding bits are enabled. 8.1.3 mode control the gpio pins can be controlled by either hardware or software. when hardware control is enabled via the gpio alternate function select (gpioafsel) register (see page 135 ), the pin state is controlled by its alternate function (that is, the peripheral). software control corresponds to gpio mode, where the gpioda t a register is used to read/write the corresponding pins. 8.1.4 pad control the pad control registers allow for gpio pad configuration by software based on the application requirements. the pad control registers include the gpiodr2r , gpiodr4r , gpiodr8r , gpioodr , gpiopur , gpiopdr , gpioslr , and gpioden registers. 8.1.5 identification the identification registers configured at reset allow software to detect and identify the module as a gpio block. the identification registers include the gpioperiphid0 - gpioperiphid7 registers as well as the gpiopcellid0 - gpiopcellid3 registers. 8.2 initialization and configuration t o use the gpio, the peripheral clock must be enabled by setting the appropriate gpio port bit field ( gpion ) in the rcgc2 register . on reset, all gpio pins (except for the five jt ag pins) default to general-purpose inut mode ( gpiodir =0 and gpioafsel =0). t able 8-1 on page 122 shows all possible configurations of the gpio pads and the control register settings required to achieve them. t able 8-2 on page 123 shows how a rising edge interrupt would be configured for pin 2 of a gpio port. t able 8-1. gpio pad configuration examples gpio register bit v alue a configuration slr dr8r dr4r dr2r pdr pur den odr dir afsel x x x x ? ? 1 0 0 0 digital input (gpio) ? ? ? ? ? ? 1 0 1 0 digital output (gpio) x x x x x x 1 1 0 0 open drain input (gpio) ? ? ? ? x x 1 1 1 0 open drain output (gpio) ? ? ? ? x x 1 1 x 1 open drain input/output (i 2 c) x x x x ? ? 1 0 x 1 digital input (t imer ccp) ? ? ? ? ? ? 1 0 x 1 digital output (t imer pwm) ? ? ? ? ? ? 1 0 x 1 digital input/output (ssi) ? ? ? ? ? ? 1 0 x 1 digital input/output (uar t) october 01, 2007 122 preliminary general-purpose input/outputs (gpios)
gpio register bit v alue a configuration slr dr8r dr4r dr2r pdr pur den odr dir afsel x x x x 0 0 0 0 0 0 analog input (comparator) ? ? ? ? ? ? 1 0 x 1 digital output (comparator) a. x=ignored (dont care bit) ?=can be either 0 or 1, depending on the configuration t able 8-2. gpio interrupt configuration example pin 2 bit v alue a desired interrupt event t rigger register 0 1 2 3 4 5 6 7 x x 0 x x x x x 0=edge 1=level gpiois x x 0 x x x x x 0=single edge 1=both edges gpioibe x x 1 x x x x x 0=low level, or negative edge 1=high level, or positive edge gpioiev 0 0 1 0 0 0 0 0 0=masked 1=not masked gpioim a. x=ignored (dont care bit) 8.3 register map t able 8-3 on page 124 lists the gpio registers. the of fset listed is a hexadecimal increment to the register s address, relative to that gpio port s base address: gpio port a: 0x4000.4000 gpio port b: 0x4000.5000 gpio port c: 0x4000.6000 gpio port d: 0x4000.7000 gpio port e: 0x4002.4000 important: the gpio registers in this chapter are duplicated in each gpio block, however , depending on the block, all eight bits may not be connected to a gpio pad. in those cases, writing to those unconnected bits has no ef fect and reading those unconnected bits returns no meaningful data. 123 october 01, 2007 preliminary lm3s600 microcontroller
note: the default reset value for the gpioafsel register is 0x0000.0000 for all gpio pins, with the exception of the five jt ag pins ( pb7 and pc[3:0] ). these five pins default to jt ag functionality . because of this, the default reset value of gpioafsel for gpio port b is 0x0000.0080 while the default reset value for port c is 0x0000.000f . t able 8-3. gpio register map see page description reset t ype name offset 126 gpio data 0x0000.0000 r/w gpioda t a 0x000 127 gpio direction 0x0000.0000 r/w gpiodir 0x400 128 gpio interrupt sense 0x0000.0000 r/w gpiois 0x404 129 gpio interrupt both edges 0x0000.0000 r/w gpioibe 0x408 130 gpio interrupt event 0x0000.0000 r/w gpioiev 0x40c 131 gpio interrupt mask 0x0000.0000 r/w gpioim 0x410 132 gpio raw interrupt status 0x0000.0000 ro gpioris 0x414 133 gpio masked interrupt status 0x0000.0000 ro gpiomis 0x418 134 gpio interrupt clear 0x0000.0000 w1c gpioicr 0x41c 135 gpio alternate function select - r/w gpioafsel 0x420 137 gpio 2-ma drive select 0x0000.00ff r/w gpiodr2r 0x500 138 gpio 4-ma drive select 0x0000.0000 r/w gpiodr4r 0x504 139 gpio 8-ma drive select 0x0000.0000 r/w gpiodr8r 0x508 140 gpio open drain select 0x0000.0000 r/w gpioodr 0x50c 141 gpio pull-up select 0x0000.00ff r/w gpiopur 0x510 142 gpio pull-down select 0x0000.0000 r/w gpiopdr 0x514 143 gpio slew rate control select 0x0000.0000 r/w gpioslr 0x518 144 gpio digital enable 0x0000.00ff r/w gpioden 0x51c 145 gpio peripheral identification 4 0x0000.0000 ro gpioperiphid4 0xfd0 146 gpio peripheral identification 5 0x0000.0000 ro gpioperiphid5 0xfd4 147 gpio peripheral identification 6 0x0000.0000 ro gpioperiphid6 0xfd8 148 gpio peripheral identification 7 0x0000.0000 ro gpioperiphid7 0xfdc 149 gpio peripheral identification 0 0x0000.0061 ro gpioperiphid0 0xfe0 150 gpio peripheral identification 1 0x0000.0000 ro gpioperiphid1 0xfe4 151 gpio peripheral identification 2 0x0000.0018 ro gpioperiphid2 0xfe8 152 gpio peripheral identification 3 0x0000.0001 ro gpioperiphid3 0xfec 153 gpio primecell identification 0 0x0000.000d ro gpiopcellid0 0xff0 154 gpio primecell identification 1 0x0000.00f0 ro gpiopcellid1 0xff4 155 gpio primecell identification 2 0x0000.0005 ro gpiopcellid2 0xff8 october 01, 2007 124 preliminary general-purpose input/outputs (gpios)
see page description reset t ype name offset 156 gpio primecell identification 3 0x0000.00b1 ro gpiopcellid3 0xffc 8.4 register descriptions the remainder of this section lists and describes the gpio registers, in numerical order by address of fset. 125 october 01, 2007 preliminary lm3s600 microcontroller
register 1: gpio data (gpioda t a), offset 0x000 the gpioda t a register is the data register . in software control mode, values written in the gpioda t a register are transferred onto the gpio port pins if the respective pins have been configured as outputs through the gpio direction (gpiodir) register (see page 127 ). in order to write to gpioda t a , the corresponding bits in the mask, resulting from the address bus bits [9:2], must be high. otherwise, the bit values remain unchanged by the write. similarly , the values read from this register are determined for each bit by the mask bit derived from the address used to access the data register , bits [9:2]. bits that are 1 in the address mask cause the corresponding bits in gpioda t a to be read, and bits that are 0 in the address mask cause the corresponding bits in gpioda t a to be read as 0, regardless of their value. a read from gpioda t a returns the last bit value written if the respective pins are configured as outputs, or it returns the value on the corresponding input pin when these are configured as inputs. all bits are cleared by a reset. gpio data (gpioda t a) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 of fset 0x000 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 da t a reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio data this register is virtually mapped to 256 locations in the address space. t o facilitate the reading and writing of data to these registers by independent drivers, the data read from and the data written to the registers are masked by the eight address lines ipaddr[9:2] . reads from this register return its current state. w rites to this register only af fect bits that are not masked by ipaddr[9:2] and are configured as outputs. see data register operation on page 120 for examples of reads and writes. 0x00 r/w da t a 7:0 october 01, 2007 126 preliminary general-purpose input/outputs (gpios)
register 2: gpio direction (gpiodir), offset 0x400 the gpiodir register is the data direction register . bits set to 1 in the gpiodir register configure the corresponding pin to be an output, while bits set to 0 configure the pins to be inputs. all bits are cleared by a reset, meaning all gpio pins are inputs by default. gpio direction (gpiodir) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 of fset 0x400 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 dir reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio data direction the dir values are defined as follows: description v alue pins are inputs. 0 pins are outputs. 1 0x00 r/w dir 7:0 127 october 01, 2007 preliminary lm3s600 microcontroller
register 3: gpio interrupt sense (gpiois), offset 0x404 the gpiois register is the interrupt sense register . bits set to 1 in gpiois configure the corresponding pins to detect levels, while bits set to 0 configure the pins to detect edges. all bits are cleared by a reset. gpio interrupt sense (gpiois) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 of fset 0x404 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 is reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio interrupt sense the is values are defined as follows: description v alue edge on corresponding pin is detected (edge-sensitive). 0 level on corresponding pin is detected (level-sensitive). 1 0x00 r/w is 7:0 october 01, 2007 128 preliminary general-purpose input/outputs (gpios)
register 4: gpio interrupt both edges (gpioibe), offset 0x408 the gpioibe register is the interrupt both-edges register . when the corresponding bit in the gpio interrupt sense (gpiois) register (see page 128 ) is set to detect edges, bits set to high in gpioibe configure the corresponding pin to detect both rising and falling edges, regardless of the corresponding bit in the gpio interrupt event (gpioiev) register (see page 130 ). clearing a bit configures the pin to be controlled by gpioiev . all bits are cleared by a reset. gpio interrupt both edges (gpioibe) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 of fset 0x408 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 ibe reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio interrupt both edges the ibe values are defined as follows: description v alue interrupt generation is controlled by the gpio interrupt event (gpioiev) register (see page 130 ). 0 both edges on the corresponding pin trigger an interrupt. 1 note: single edge is determined by the corresponding bit in gpioiev . 0x00 r/w ibe 7:0 129 october 01, 2007 preliminary lm3s600 microcontroller
register 5: gpio interrupt event (gpioiev), offset 0x40c the gpioiev register is the interrupt event register . bits set to high in gpioiev configure the corresponding pin to detect rising edges or high levels, depending on the corresponding bit value in the gpio interrupt sense (gpiois) register (see page 128 ). clearing a bit configures the pin to detect falling edges or low levels, depending on the corresponding bit value in gpiois . all bits are cleared by a reset. gpio interrupt event (gpioiev) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 of fset 0x40c t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 iev reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio interrupt event the iev values are defined as follows: description v alue falling edge or low levels on corresponding pins trigger interrupts. 0 rising edge or high levels on corresponding pins trigger interrupts. 1 0x00 r/w iev 7:0 october 01, 2007 130 preliminary general-purpose input/outputs (gpios)
register 6: gpio interrupt mask (gpioim), offset 0x410 the gpioim register is the interrupt mask register . bits set to high in gpioim allow the corresponding pins to trigger their individual interrupts and the combined gpiointr line. clearing a bit disables interrupt triggering on that pin. all bits are cleared by a reset. gpio interrupt mask (gpioim) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 of fset 0x410 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 ime reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio interrupt mask enable the ime values are defined as follows: description v alue corresponding pin interrupt is masked. 0 corresponding pin interrupt is not masked. 1 0x00 r/w ime 7:0 131 october 01, 2007 preliminary lm3s600 microcontroller
register 7: gpio raw interrupt status (gpioris), offset 0x414 the gpioris register is the raw interrupt status register . bits read high in gpioris reflect the status of interrupt trigger conditions detected (raw , prior to masking), indicating that all the requirements have been met, before they are finally allowed to trigger by the gpio interrupt mask (gpioim) register (see page 131 ). bits read as zero indicate that corresponding input pins have not initiated an interrupt. all bits are cleared by a reset. gpio raw interrupt status (gpioris) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 of fset 0x414 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 ris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio interrupt raw status reflects the status of interrupt trigger condition detection on pins (raw , prior to masking). the ris values are defined as follows: description v alue corresponding pin interrupt requirements not met. 0 corresponding pin interrupt has met requirements. 1 0x00 ro ris 7:0 october 01, 2007 132 preliminary general-purpose input/outputs (gpios)
register 8: gpio masked interrupt status (gpiomis), offset 0x418 the gpiomis register is the masked interrupt status register . bits read high in gpiomis reflect the status of input lines triggering an interrupt. bits read as low indicate that either no interrupt has been generated, or the interrupt is masked. gpiomis is the state of the interrupt after masking. gpio masked interrupt status (gpiomis) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 of fset 0x418 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 mis reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio masked interrupt status masked value of interrupt due to corresponding pin. the mis values are defined as follows: description v alue corresponding gpio line interrupt not active. 0 corresponding gpio line asserting interrupt. 1 0x00 ro mis 7:0 133 october 01, 2007 preliminary lm3s600 microcontroller
register 9: gpio interrupt clear (gpioicr), offset 0x41c the gpioicr register is the interrupt clear register . w riting a 1 to a bit in this register clears the corresponding interrupt edge detection logic register . w riting a 0 has no ef fect. gpio interrupt clear (gpioicr) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 of fset 0x41c t ype w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 ic reserved w1c w1c w1c w1c w1c w1c w1c w1c ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio interrupt clear the ic values are defined as follows: description v alue corresponding interrupt is unaf fected. 0 corresponding interrupt is cleared. 1 0x00 w1c ic 7:0 october 01, 2007 134 preliminary general-purpose input/outputs (gpios)
register 10: gpio alternate function select (gpioafsel), offset 0x420 the gpioafsel register is the mode control select register . w riting a 1 to any bit in this register selects the hardware control for the corresponding gpio line. all bits are cleared by a reset, therefore no gpio line is set to hardware control by default. important: all gpio pins are inputs by default ( gpiodir =0 and gpioafsel =0), with the exception of the five jt ag pins ( pb7 and pc[3:0] ). the jt ag pins default to their jt ag functionality ( gpioafsel =1). a power-on-reset ( por ) or asserting an external reset ( rst ) puts both groups of pins back to their default state. caution C if the jt ag pins ar e used as gpios in a design, pb7 and pc2 cannot have external pull-down r esistors connected to both of them at the same time. if both pins ar e pulled low during r eset, the contr oller has unpr edictable behavior . if this happens, r emove one or both of the pull-down r esistors, and apply rst or power-cycle the part. in addition, it is possible to cr eate a softwar e sequence that pr events the debugger fr om connecting to the stellaris ? micr ocontr oller . if the pr ogram code loaded into fash immediately changes the jt ag pins to their gpio functionality , the debugger may not have enough time to connect and halt the contr oller befor e the jt ag pin functionality switches. this may lock the debugger out of the part. this can be avoided with a softwar e r outine that r estor es jt ag functionality based on an external or softwar e trigger . gpio alternate function select (gpioafsel) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 of fset 0x420 t ype r/w , reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 afsel reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype - - - - - - - - 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 135 october 01, 2007 preliminary lm3s600 microcontroller
description reset t ype name bit/field gpio alternate function select the afsel values are defined as follows: description v alue software control of corresponding gpio line (gpio mode). 0 hardware control of corresponding gpio line (alternate hardware function). 1 note: the default reset value for the gpioafsel register is 0x0000.0000 for all gpio pins, with the exception of the five jt ag pins ( pb7 and pc[3:0] ). these five pins default to jt ag functionality . because of this, the default reset value of gpioafsel for gpio port b is 0x0000.0080 while the default reset value for port c is 0x0000.000f . - r/w afsel 7:0 october 01, 2007 136 preliminary general-purpose input/outputs (gpios)
register 1 1: gpio 2-ma drive select (gpiodr2r), offset 0x500 the gpiodr2r register is the 2-ma drive control register . it allows for each gpio signal in the port to be individually configured without af fecting the other pads. when writing a drv2 bit for a gpio signal, the corresponding drv4 bit in the gpiodr4r register and the drv8 bit in the gpiodr8r register are automatically cleared by hardware. gpio 2-ma drive select (gpiodr2r) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 of fset 0x500 t ype r/w , reset 0x0000.00ff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 dr v2 reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 output pad 2-ma drive enable a write of 1 to either gpiodr4[n] or gpiodr8[n] clears the corresponding 2-ma enable bit. the change is ef fective on the second clock cycle after the write. 0xff r/w dr v2 7:0 137 october 01, 2007 preliminary lm3s600 microcontroller
register 12: gpio 4-ma drive select (gpiodr4r), offset 0x504 the gpiodr4r register is the 4-ma drive control register . it allows for each gpio signal in the port to be individually configured without af fecting the other pads. when writing the drv4 bit for a gpio signal, the corresponding drv2 bit in the gpiodr2r register and the drv8 bit in the gpiodr8r register are automatically cleared by hardware. gpio 4-ma drive select (gpiodr4r) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 of fset 0x504 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 dr v4 reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 output pad 4-ma drive enable a write of 1 to either gpiodr2[n] or gpiodr8[n] clears the corresponding 4-ma enable bit. the change is ef fective on the second clock cycle after the write. 0x00 r/w dr v4 7:0 october 01, 2007 138 preliminary general-purpose input/outputs (gpios)
register 13: gpio 8-ma drive select (gpiodr8r), offset 0x508 the gpiodr8r register is the 8-ma drive control register . it allows for each gpio signal in the port to be individually configured without af fecting the other pads. when writing the drv8 bit for a gpio signal, the corresponding drv2 bit in the gpiodr2r register and the drv4 bit in the gpiodr4r register are automatically cleared by hardware. gpio 8-ma drive select (gpiodr8r) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 of fset 0x508 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 dr v8 reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 output pad 8-ma drive enable a write of 1 to either gpiodr2[n] or gpiodr4[n] clears the corresponding 8-ma enable bit. the change is ef fective on the second clock cycle after the write. 0x00 r/w dr v8 7:0 139 october 01, 2007 preliminary lm3s600 microcontroller
register 14: gpio open drain select (gpioodr), offset 0x50c the gpioodr register is the open drain control register . setting a bit in this register enables the open drain configuration of the corresponding gpio pad. when open drain mode is enabled, the corresponding bit should also be set in the gpio digital input enable (gpioden) register (see page 144 ). corresponding bits in the drive strength registers ( gpiodr2r , gpiodr4r , gpiodr8r , and gpioslr ) can be set to achieve the desired rise and fall times. the gpio acts as an open drain input if the corresponding bit in the gpiodir register is set to 0; and as an open drain output when set to 1. when using the i 2 c module, the gpio alternate function select (gpioafsel) register bit for pb2 and pb3 should be set to 1 (see examples in initialization and configuration on page 122 ). gpio open drain select (gpioodr) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 of fset 0x50c t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 ode reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 output pad open drain enable the ode values are defined as follows: description v alue open drain configuration is disabled. 0 open drain configuration is enabled. 1 0x00 r/w ode 7:0 october 01, 2007 140 preliminary general-purpose input/outputs (gpios)
register 15: gpio pull-up select (gpiopur), offset 0x510 the gpiopur register is the pull-up control register . when a bit is set to 1, it enables a weak pull-up resistor on the corresponding gpio signal. setting a bit in gpiopur automatically clears the corresponding bit in the gpio pull-down select (gpiopdr) register (see page 142 ). gpio pull-up select (gpiopur) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 of fset 0x510 t ype r/w , reset 0x0000.00ff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pue reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 pad w eak pull-up enable a write of 1 to gpiopdr[n] clears the corresponding gpiopur[n] enables. the change is ef fective on the second clock cycle after the write. 0xff r/w pue 7:0 141 october 01, 2007 preliminary lm3s600 microcontroller
register 16: gpio pull-down select (gpiopdr), offset 0x514 the gpiopdr register is the pull-down control register . when a bit is set to 1, it enables a weak pull-down resistor on the corresponding gpio signal. setting a bit in gpiopdr automatically clears the corresponding bit in the gpio pull-up select (gpiopur) register (see page 141 ). gpio pull-down select (gpiopdr) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 of fset 0x514 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pde reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 pad w eak pull-down enable a write of 1 to gpiopur[n] clears the corresponding gpiopdr[n] enables. the change is ef fective on the second clock cycle after the write. 0x00 r/w pde 7:0 october 01, 2007 142 preliminary general-purpose input/outputs (gpios)
register 17: gpio slew rate control select (gpioslr), offset 0x518 the gpioslr register is the slew rate control register . slew rate control is only available when using the 8-ma drive strength option via the gpio 8-ma drive select (gpiodr8r) register (see page 139 ). gpio slew rate control select (gpioslr) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 of fset 0x518 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 srl reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 slew rate limit enable (8-ma drive only) the srl values are defined as follows: description v alue slew rate control disabled. 0 slew rate control enabled. 1 0x00 r/w srl 7:0 143 october 01, 2007 preliminary lm3s600 microcontroller
register 18: gpio digital enable (gpioden), offset 0x51c the gpioden register is the digital input enable register . by default, all gpio signals are configured as digital inputs at reset. if a pin is being used as a gpio or its alternate hardware function, it should be configured as a digital input. the only time that a pin should not be configured as a digital input is when the gpio pin is configured to be one of the analog input signals for the analog comparators. gpio digital enable (gpioden) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 of fset 0x51c t ype r/w , reset 0x0000.00ff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 den reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 digital enable the den values are defined as follows: description v alue digital functions disabled. 0 digital functions enabled. 1 0xff r/w den 7:0 october 01, 2007 144 preliminary general-purpose input/outputs (gpios)
register 19: gpio peripheral identification 4 (gpioperiphid4), offset 0xfd0 the gpioperiphid4 , gpioperiphid5 , gpioperiphid6 , and gpioperiphid7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register , used by software to identify the peripheral. gpio peripheral identification 4 (gpioperiphid4) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 of fset 0xfd0 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid4 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio peripheral id register[7:0] 0x00 ro pid4 7:0 145 october 01, 2007 preliminary lm3s600 microcontroller
register 20: gpio peripheral identification 5 (gpioperiphid5), offset 0xfd4 the gpioperiphid4 , gpioperiphid5 , gpioperiphid6 , and gpioperiphid7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register , used by software to identify the peripheral. gpio peripheral identification 5 (gpioperiphid5) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 of fset 0xfd4 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid5 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio peripheral id register[15:8] 0x00 ro pid5 7:0 october 01, 2007 146 preliminary general-purpose input/outputs (gpios)
register 21: gpio peripheral identification 6 (gpioperiphid6), offset 0xfd8 the gpioperiphid4 , gpioperiphid5 , gpioperiphid6 , and gpioperiphid7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register , used by software to identify the peripheral. gpio peripheral identification 6 (gpioperiphid6) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 of fset 0xfd8 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid6 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio peripheral id register[23:16] 0x00 ro pid6 7:0 147 october 01, 2007 preliminary lm3s600 microcontroller
register 22: gpio peripheral identification 7 (gpioperiphid7), offset 0xfdc the gpioperiphid4 , gpioperiphid5 , gpioperiphid6 , and gpioperiphid7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register , used by software to identify the peripheral. gpio peripheral identification 7 (gpioperiphid7) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 of fset 0xfdc t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid7 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio peripheral id register[31:24] 0x00 ro pid7 7:0 october 01, 2007 148 preliminary general-purpose input/outputs (gpios)
register 23: gpio peripheral identification 0 (gpioperiphid0), offset 0xfe0 the gpioperiphid0 , gpioperiphid1 , gpioperiphid2 , and gpioperiphid3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register , used by software to identify the peripheral. gpio peripheral identification 0 (gpioperiphid0) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 of fset 0xfe0 t ype ro, reset 0x0000.0061 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio peripheral id register[7:0] can be used by software to identify the presence of this peripheral. 0x61 ro pid0 7:0 149 october 01, 2007 preliminary lm3s600 microcontroller
register 24: gpio peripheral identification 1 (gpioperiphid1), offset 0xfe4 the gpioperiphid0 , gpioperiphid1 , gpioperiphid2 , and gpioperiphid3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register , used by software to identify the peripheral. gpio peripheral identification 1 (gpioperiphid1) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 of fset 0xfe4 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio peripheral id register[15:8] can be used by software to identify the presence of this peripheral. 0x00 ro pid1 7:0 october 01, 2007 150 preliminary general-purpose input/outputs (gpios)
register 25: gpio peripheral identification 2 (gpioperiphid2), offset 0xfe8 the gpioperiphid0 , gpioperiphid1 , gpioperiphid2 , and gpioperiphid3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register , used by software to identify the peripheral. gpio peripheral identification 2 (gpioperiphid2) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 of fset 0xfe8 t ype ro, reset 0x0000.0018 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio peripheral id register[23:16] can be used by software to identify the presence of this peripheral. 0x18 ro pid2 7:0 151 october 01, 2007 preliminary lm3s600 microcontroller
register 26: gpio peripheral identification 3 (gpioperiphid3), offset 0xfec the gpioperiphid0 , gpioperiphid1 , gpioperiphid2 , and gpioperiphid3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register , used by software to identify the peripheral. gpio peripheral identification 3 (gpioperiphid3) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 of fset 0xfec t ype ro, reset 0x0000.0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio peripheral id register[31:24] can be used by software to identify the presence of this peripheral. 0x01 ro pid3 7:0 october 01, 2007 152 preliminary general-purpose input/outputs (gpios)
register 27: gpio primecell identification 0 (gpiopcellid0), offset 0xff0 the gpiopcellid0 , gpiopcellid1 , gpiopcellid2 , and gpiopcellid3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register . the register is used as a standard cross-peripheral identification system. gpio primecell identification 0 (gpiopcellid0) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 of fset 0xff0 t ype ro, reset 0x0000.000d 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio primecell id register[7:0] provides software a standard cross-peripheral identification system. 0x0d ro cid0 7:0 153 october 01, 2007 preliminary lm3s600 microcontroller
register 28: gpio primecell identification 1 (gpiopcellid1), offset 0xff4 the gpiopcellid0 , gpiopcellid1 , gpiopcellid2 , and gpiopcellid3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register . the register is used as a standard cross-peripheral identification system. gpio primecell identification 1 (gpiopcellid1) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 of fset 0xff4 t ype ro, reset 0x0000.00f0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio primecell id register[15:8] provides software a standard cross-peripheral identification system. 0xf0 ro cid1 7:0 october 01, 2007 154 preliminary general-purpose input/outputs (gpios)
register 29: gpio primecell identification 2 (gpiopcellid2), offset 0xff8 the gpiopcellid0 , gpiopcellid1 , gpiopcellid2 , and gpiopcellid3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register . the register is used as a standard cross-peripheral identification system. gpio primecell identification 2 (gpiopcellid2) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 of fset 0xff8 t ype ro, reset 0x0000.0005 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio primecell id register[23:16] provides software a standard cross-peripheral identification system. 0x05 ro cid2 7:0 155 october 01, 2007 preliminary lm3s600 microcontroller
register 30: gpio primecell identification 3 (gpiopcellid3), offset 0xffc the gpiopcellid0 , gpiopcellid1 , gpiopcellid2 , and gpiopcellid3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register . the register is used as a standard cross-peripheral identification system. gpio primecell identification 3 (gpiopcellid3) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 of fset 0xffc t ype ro, reset 0x0000.00b1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio primecell id register[31:24] provides software a standard cross-peripheral identification system. 0xb1 ro cid3 7:0 october 01, 2007 156 preliminary general-purpose input/outputs (gpios)
9 general-purpose t imers programmable timers can be used to count or time external events that drive the t imer input pins. the stellaris ? general-purpose t imer module (gptm) contains three gptm blocks (t imer0, t imer1, and t imer 2). each gptm block provides two 16-bit timer/counters (referred to as t imera and t imerb) that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit real-t ime clock (r tc). note: t imer2 is an internal timer and can only be used to generate internal interrupts. the general-purpose t imer module is one timing resource available on the stellaris ? microcontrollers. other timer resources include the system t imer (syst ick) (see system t imer (syst ick) on page 31 ). the following modes are supported: 32-bit t imer modes C programmable one-shot timer C programmable periodic timer C real-t ime clock using 32.768-khz input clock C software-controlled event stalling (excluding r tc mode) 16-bit t imer modes C general-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes only) C programmable one-shot timer C programmable periodic timer C software-controlled event stalling 16-bit input capture modes C input edge count capture C input edge time capture 16-bit pwm mode C simple pwm mode with software-programmable output inversion of the pwm signal 157 october 01, 2007 preliminary lm3s600 microcontroller
9.1 block diagram figure 9-1. gptm module block diagram 9.2 functional description the main components of each gptm block are two free-running 16-bit up/down counters (referred to as t imera and t imerb), two 16-bit match registers, two prescaler match registers, and two 16-bit load/initialization registers and their associated control functions. the exact functionality of each gptm is controlled by software and configured through the register interface. software configures the gptm using the gptm configuration (gptmcfg) register (see page 169 ), the gptm t imera mode (gptmt amr) register (see page 170 ), and the gptm t imerb mode (gptmtbmr) register (see page 172 ). when in one of the 32-bit modes, the timer can only act as a 32-bit timer . however , when configured in 16-bit mode, the gptm can have its two 16-bit timers configured in any combination of the 16-bit modes. 9.2.1 gptm reset conditions after reset has been applied to the gptm module, the module is in an inactive state, and all control registers are cleared and in their default states. counters t imera and t imerb are initialized to 0xffff , along with their corresponding load registers: the gptm t imera interval load (gptmt ailr) register (see page 183 ) and the gptm t imerb interval load (gptmtbilr) register (see page 184 ). the prescale counters are initialized to 0x00: the gptm t imera prescale (gptmt apr) register (see page 187 ) and the gptm t imerb prescale (gptmtbpr) register (see page 188 ). 9.2.2 32-bit t imer operating modes note: both the odd- and even-numbered ccp pins are used for 16-bit mode. only the even-numbered ccp pins are used for 32-bit mode. october 01, 2007 158 preliminary general-purpose t imers t a comparator tb comparator gptmtbr gptmar clock / edge detect r tc divider clock / edge detect t imera interrupt t imerb interrupt system clock 0x0000 (down counter modes) 0x0000 (down counter modes) ccp (even) ccp (odd) en en t imera control gptmt apmr gptmt ailr gptmt ama tchr gptmt apr gptmt amr t imerb control gptmtbpmr gptmtbilr gptmtbma tchr gptmtbpr gptmtbmr interrupt / config gptmcfg gptmris gptmicr gptmmis gptmimr gptmctl
this section describes the three gptm 32-bit timer modes (one-shot, periodic, and r tc) and their configuration. the gptm is placed into 32-bit mode by writing a 0 (one-shot/periodic 32-bit timer mode) or a 1 (r tc mode) to the gptm configuration (gptmcfg) register . in both configurations, certain gptm registers are concatenated to form pseudo 32-bit registers. these registers include: gptm t imera interval load (gptmt ailr) register [15:0], see page 183 gptm t imerb interval load (gptmtbilr) register [15:0], see page 184 gptm t imera (gptmt ar) register [15:0], see page 191 gptm t imerb (gptmtbr) register [15:0], see page 192 in the 32-bit modes, the gptm translates a 32-bit write access to gptmt ailr into a write access to both gptmt ailr and gptmtbilr . the resulting word ordering for such a write operation is: gptmtbilr[15:0]:gptmtailr[15:0] likewise, a read access to gptmt ar returns the value: gptmtbr[15:0]:gptmtar[15:0] 9.2.2.1 32-bit one-shot/periodic t imer mode in 32-bit one-shot and periodic timer modes, the concatenated versions of the t imera and t imerb registers are configured as a 32-bit down-counter . the selection of one-shot or periodic mode is determined by the value written to the tamr field of the gptm t imera mode (gptmt amr) register (see page 170 ), and there is no need to write to the gptm t imerb mode (gptmtbmr) register . when software writes the taen bit in the gptm control (gptmctl) register (see page 174 ), the timer begins counting down from its preloaded value. once the 0x0000.0000 state is reached, the timer reloads its start value from the concatenated gptmt ailr on the next cycle. if configured to be a one-shot timer , the timer stops counting and clears the taen bit in the gptmctl register . if configured as a periodic timer , it continues counting. in addition to reloading the count value, the gptm generates interrupts and output triggers when it reaches the 0x0000000 state. the gptm sets the tatoris bit in the gptm raw interrupt status (gptmris) register (see page 179 ), and holds it until it is cleared by writing the gptm interrupt clear (gptmicr) register (see page 181 ). if the time-out interrupt is enabled in the gptm interrupt mask (gptimr) register (see page 177 ), the gptm also sets the tatomis bit in the gptm masked interrupt status (gptmmis) register (see page 180 ). the output trigger is a one-clock-cycle pulse that is asserted when the counter hits the 0x0000.0000 state, and deasserted on the following clock cycle. it is enabled by setting the taote bit in gptmctl . if software reloads the gptmt ailr register while the counter is running, the counter loads the new value on the next clock cycle and continues counting from the new value. if the tastall bit in the gptmctl register is asserted, the timer freezes counting until the signal is deasserted. 9.2.2.2 32-bit real-t ime clock t imer mode in real-t ime clock (r tc) mode, the concatenated versions of the t imera and t imerb registers are configured as a 32-bit up-counter . when r tc mode is selected for the first time, the counter is 159 october 01, 2007 preliminary lm3s600 microcontroller
loaded with a value of 0x0000.0001. all subsequent load values must be written to the gptm t imera match (gptmt ama tchr) register (see page 185 ) by the controller . the input clock on the ccp0 , ccp2 , or ccp4 pins is required to be 32.768 khz in r tc mode. the clock signal is then divided down to a 1 hz rate and is passed along to the input of the 32-bit counter . when software writes the taen bit inthe gptmctl register , the counter starts counting up from its preloaded value of 0x0000.0001. when the current count value matches the preloaded value in the gptmt ama tchr register , it rolls over to a value of 0x0000.0000 and continues counting until either a hardware reset, or it is disabled by software (clearing the taen bit). when a match occurs, the gptm asserts the rtcris bit in gptmris . if the r tc interrupt is enabled in gptimr , the gptm also sets the rtcmis bit in gptmisr and generates a controller interrupt. the status flags are cleared by writing the rtccint bit in gptmicr . if the tastall and/or tbstall bits in the gptmctl register are set, the timer does not freeze if the rtcen bit is set in gptmctl . 9.2.3 16-bit t imer operating modes the gptm is placed into global 16-bit mode by writing a value of 0x4 to the gptm configuration (gptmcfg) register (see page 169 ). this section describes each of the gptm 16-bit modes of operation. t imera and t imerb have identical modes, so a single description is given using an n to reference both. 9.2.3.1 16-bit one-shot/periodic t imer mode in 16-bit one-shot and periodic timer modes, the timer is configured as a 16-bit down-counter with an optional 8-bit prescaler that ef fectively extends the counting range of the timer to 24 bits. the selection of one-shot or periodic mode is determined by the value written to the tnmr field of the gptmtnmr register . the optional prescaler is loaded into the gptm t imern prescale (gptmtnpr) register . when software writes the tnen bit in the gptmctl register , the timer begins counting down from its preloaded value. once the 0x0000 state is reached, the timer reloads its start value from gptmtnilr and gptmtnpr on the next cycle. if configured to be a one-shot timer , the timer stops counting and clears the tnen bit in the gptmctl register . if configured as a periodic timer , it continues counting. in addition to reloading the count value, the timer generates interrupts and output triggers when it reaches the 0x0000 state. the gptm sets the tntoris bit in the gptmris register , and holds it until it is cleared by writing the gptmicr register . if the time-out interrupt is enabled in gptimr , the gptm also sets the tntomis bit in gptmisr and generates a controller interrupt. the output trigger is a one-clock-cycle pulse that is asserted when the counter hits the 0x0000 state, and deasserted on the following clock cycle. it is enabled by setting the tnote bit in the gptmctl register , and can trigger soc-level events. if software reloads the gptmt ailr register while the counter is running, the counter loads the new value on the next clock cycle and continues counting from the new value. if the tnstall bit in the gptmctl register is enabled, the timer freezes counting until the signal is deasserted. the following example shows a variety of configurations for a 16-bit free running timer while using the prescaler . all values assume a 50-mhz clock with t c=20 ns (clock period). october 01, 2007 160 preliminary general-purpose t imers
t able 9-1. 16-bit t imer w ith prescaler configurations units max t ime #clock (t c) a prescale ms 1.3107 1 00000000 ms 2.6214 2 00000001 ms 3.9321 3 00000010 -- -- -- ------------ ms 332.9229 254 1 1 1 1 1 100 ms 334.2336 255 1 1 1 1 1 1 10 ms 335.5443 256 1 1 1 1 1 1 1 1 a. t c is the clock period. 9.2.3.2 16-bit input edge count mode in edge count mode, the timer is configured as a down-counter capable of capturing three types of events: rising edge, falling edge, or both. t o place the timer in edge count mode, the tncmr bit of the gptmtnmr register must be set to 0. the type of edge that the timer counts is determined by the tnevent fields of the gptmctl register . during initialization, the gptm t imern match (gptmtnma tchr) register is configured so that the dif ference between the value in the gptmtnilr register and the gptmtnma tchr register equals the number of edge events that must be counted. when software writes the tnen bit in the gptm control (gptmctl) register , the timer is enabled for event capture. each input event on the ccp pin decrements the counter by 1 until the event count matches gptmtnma tchr . when the counts match, the gptm asserts the cnmris bit in the gptmris register (and the cnmmis bit, if the interrupt is not masked). the counter is then reloaded using the value in gptmtnilr , and stopped since the gptm automatically clears the tnen bit in the gptmctl register . once the event count has been reached, all further events are ignored until tnen is re-enabled by software. figure 9-2 on page 162 shows how input edge count mode works. in this case, the timer start value is set to gptmnilr =0x000a and the match value is set to gptmnma tchr =0x0006 so that four edge events are counted. the counter is configured to detect both edges of the input signal. note that the last two edges are not counted since the timer automatically clears the tnen bit after the current count matches the value in the gptmnmr register . 161 october 01, 2007 preliminary lm3s600 microcontroller
figure 9-2. 16-bit input edge count mode example 9.2.3.3 16-bit input edge t ime mode note: the prescaler is not available in 16-bit input edge t ime mode. in edge t ime mode, the timer is configured as a free-running down-counter initialized to the value loaded in the gptmtnilr register (or 0xffff at reset). this mode allows for event capture of both rising and falling edges. the timer is placed into edge t ime mode by setting the tncmr bit in the gptmtnmr register , and the type of event that the timer captures is determined by the tnevent fields of the gptmcntl register . when software writes the tnen bit in the gptmctl register , the timer is enabled for event capture. when the selected input event is detected, the current tn counter value is captured in the gptmtnr register and is available to be read by the controller . the gptm then asserts the cneris bit (and the cnemis bit, if the interrupt is not masked). after an event has been captured, the timer does not stop counting. it continues to count until the tnen bit is cleared. when the timer reaches the 0x0000 state, it is reloaded with the value from the gptmnilr register . figure 9-3 on page 163 shows how input edge timing mode works. in the diagram, it is assumed that the start value of the timer is the default value of 0xffff , and the timer is configured to capture rising edge events. each time a rising edge event is detected, the current count value is loaded into the gptmtnr register , and is held there until another rising edge is detected (at which point the new count value is loaded into gptmtnr ). october 01, 2007 162 preliminary general-purpose t imers 0x000a 0x0006 0x0007 0x0008 0x0009 input signal t imer stops, flags asserted t imer reload on next cycle ignored ignored count
figure 9-3. 16-bit input edge t ime mode example 9.2.3.4 16-bit pwm mode the gptm supports a simple pwm generation mode. in pwm mode, the timer is configured as a down-counter with a start value (and thus period) defined by gptmtnilr . pwm mode is enabled with the gptmtnmr register by setting the tnams bit to 0x1, the tncmr bit to 0x0, and the tnmr field to 0x2. when software writes the tnen bit in the gptmctl register , the counter begins counting down until it reaches the 0x0000 state. on the next counter cycle, the counter reloads its start value from gptmtnilr (and gptmtnpr if using a prescaler) and continues counting until disabled by software clearing the tnen bit in the gptmctl register . no interrupts or status bits are asserted in pwm mode. the output pwm signal asserts when the counter is at the value of the gptmtnilr register (its start state), and is deasserted when the counter value equals the value in the gptm t imern match register (gptmnma tchr) . software has the capability of inverting the output pwm signal by setting the tnpwml bit in the gptmctl register . figure 9-4 on page 164 shows how to generate an output pwm with a 1-ms period and a 66% duty cycle assuming a 50-mhz input clock and tnpwml =0 (duty cycle would be 33% for the tnpwml =1 configuration). for this example, the start value is gptmnirl =0xc350 and the match value is gptmnmr =0x41 1a. 163 october 01, 2007 preliminary lm3s600 microcontroller gptmtnr=y input signal t ime count gptmtnr=x gptmtnr=z z x y 0xffff
figure 9-4. 16-bit pwm mode example 9.3 initialization and configuration t o use the general-purpose timers, the peripheral clock must be enabled by setting the timer0 , timer1 , and timer2 bits in the rcgc1 register . this section shows module initialization and configuration examples for each of the supported timer modes. 9.3.1 32-bit one-shot/periodic t imer mode the gptm is configured for 32-bit one-shot and periodic modes by the following sequence: 1. ensure the timer is disabled (the taen bit in the gptmctl register is cleared) before making any changes. 2. w rite the gptm configuration register (gptmcfg) with a value of 0x0. 3. set the tamr field in the gptm t imera mode register (gptmt amr) : a. w rite a value of 0x1 for one-shot mode. b. w rite a value of 0x2 for periodic mode. 4. load the start value into the gptm t imera interval load register (gptmt ailr) . 5. if interrupts are required, set the tatoim bit in the gptm interrupt mask register (gptmimr) . 6. set the taen bit in the gptmctl register to enable the timer and start counting. october 01, 2007 164 preliminary general-purpose t imers output signal t ime count gptmtnr=gptmnmr gptmtnr=gptmnmr 0xc350 0x41 1a tnpwml = 0 tnpwml = 1 tnen set
7. poll the tatoris bit in the gptmris register or wait for the interrupt to be generated (if enabled). in both cases, the status flags are cleared by writing a 1 to the tatocint bit of the gptm interrupt clear register (gptmicr) . in one-shot mode, the timer stops counting after step 7 on page 165 . t o re-enable the timer , repeat the sequence. a timer configured in periodic mode does not stop counting after it times out. 9.3.2 32-bit real-t ime clock (rtc) mode t o use the r tc mode, the timer must have a 32.768-khz input signal on its ccp0 , ccp2 , or ccp4 pins. t o enable the r tc feature, follow these steps: 1. ensure the timer is disabled (the taen bit is cleared) before making any changes. 2. w rite the gptm configuration register (gptmcfg) with a value of 0x1. 3. w rite the desired match value to the gptm t imera match register (gptmt ama tchr) . 4. set/clear the rtcen bit in the gptm control register (gptmctl) as desired. 5. if interrupts are required, set the rtcim bit in the gptm interrupt mask register (gptmimr) . 6. set the taen bit in the gptmctl register to enable the timer and start counting. when the timer count equals the value in the gptmt ama tchr register , the counter is re-loaded with 0x0000.0000 and begins counting. if an interrupt is enabled, it does not have to be cleared. 9.3.3 16-bit one-shot/periodic t imer mode a timer is configured for 16-bit one-shot and periodic modes by the following sequence: 1. ensure the timer is disabled (the tnen bit is cleared) before making any changes. 2. w rite the gptm configuration register (gptmcfg) with a value of 0x4. 3. set the tnmr field in the gptm t imer mode (gptmtnmr) register: a. w rite a value of 0x1 for one-shot mode. b. w rite a value of 0x2 for periodic mode. 4. if a prescaler is to be used, write the prescale value to the gptm t imern prescale register (gptmtnpr) . 5. load the start value into the gptm t imer interval load register (gptmtnilr) . 6. if interrupts are required, set the tntoim bit in the gptm interrupt mask register (gptmimr) . 7. set the tnen bit in the gptm control register (gptmctl) to enable the timer and start counting. 8. poll the tntoris bit in the gptmris register or wait for the interrupt to be generated (if enabled). in both cases, the status flags are cleared by writing a 1 to the tntocint bit of the gptm interrupt clear register (gptmicr) . 165 october 01, 2007 preliminary lm3s600 microcontroller
in one-shot mode, the timer stops counting after step 8 on page 165 . t o re-enable the timer , repeat the sequence. a timer configured in periodic mode does not stop counting after it times out. 9.3.4 16-bit input edge count mode a timer is configured to input edge count mode by the following sequence: 1. ensure the timer is disabled (the tnen bit is cleared) before making any changes. 2. w rite the gptm configuration (gptmcfg) register with a value of 0x4. 3. in the gptm t imer mode (gptmtnmr) register , write the tncmr field to 0x0 and the tnmr field to 0x3. 4. configure the type of event(s) that the timer captures by writing the tnevent field of the gptm control (gptmctl) register . 5. load the timer start value into the gptm t imern interval load (gptmtnilr) register . 6. load the desired event count into the gptm t imern match (gptmtnma tchr) register . 7. if interrupts are required, set the cnmim bit in the gptm interrupt mask (gptmimr) register . 8. set the tnen bit in the gptmctl register to enable the timer and begin waiting for edge events. 9. poll the cnmris bit in the gptmris register or wait for the interrupt to be generated (if enabled). in both cases, the status flags are cleared by writing a 1 to the cnmcint bit of the gptm interrupt clear (gptmicr) register . in input edge count mode, the timer stops after the desired number of edge events has been detected. t o re-enable the timer , ensure that the tnen bit is cleared and repeat step 4 on page 166 - step 9 on page 166 . 9.3.5 16-bit input edge t iming mode a timer is configured to input edge t iming mode by the following sequence: 1. ensure the timer is disabled (the tnen bit is cleared) before making any changes. 2. w rite the gptm configuration (gptmcfg) register with a value of 0x4. 3. in the gptm t imer mode (gptmtnmr) register , write the tncmr field to 0x1 and the tnmr field to 0x3. 4. configure the type of event that the timer captures by writing the tnevent field of the gptm control (gptmctl) register . 5. load the timer start value into the gptm t imern interval load (gptmtnilr) register . 6. if interrupts are required, set the cneim bit in the gptm interrupt mask (gptmimr) register . 7. set the tnen bit in the gptm control (gptmctl) register to enable the timer and start counting. 8. poll the cneris bit in the gptmris register or wait for the interrupt to be generated (if enabled). in both cases, the status flags are cleared by writing a 1 to the cnecint bit of the gptm october 01, 2007 166 preliminary general-purpose t imers
interrupt clear (gptmicr) register . the time at which the event happened can be obtained by reading the gptm t imern (gptmtnr) register . in input edge t iming mode, the timer continues running after an edge event has been detected, but the timer interval can be changed at any time by writing the gptmtnilr register . the change takes ef fect at the next cycle after the write. 9.3.6 16-bit pwm mode a timer is configured to pwm mode using the following sequence: 1. ensure the timer is disabled (the tnen bit is cleared) before making any changes. 2. w rite the gptm configuration (gptmcfg) register with a value of 0x4. 3. in the gptm t imer mode (gptmtnmr) register , set the tnams bit to 0x1, the tncmr bit to 0x0, and the tnmr field to 0x2. 4. configure the output state of the pwm signal (whether or not it is inverted) in the tnevent field of the gptm control (gptmctl) register . 5. load the timer start value into the gptm t imern interval load (gptmtnilr) register . 6. load the gptm t imern match (gptmtnma tchr) register with the desired value. 7. if a prescaler is going to be used, configure the gptm t imern prescale (gptmtnpr) register and the gptm t imern prescale match (gptmtnpmr) register . 8. set the tnen bit in the gptm control (gptmctl) register to enable the timer and begin generation of the output pwm signal. in pwm t iming mode, the timer continues running after the pwm signal has been generated. the pwm period can be adjusted at any time by writing the gptmtnilr register , and the change takes ef fect at the next cycle after the write. 9.4 register map t able 9-2 on page 167 lists the gptm registers. the of fset listed is a hexadecimal increment to the register s address, relative to that timer s base address: t imer0: 0x4003.0000 t imer1: 0x4003.1000 t imer2: 0x4003.2000 t able 9-2. t imers register map see page description reset t ype name offset 169 gptm configuration 0x0000.0000 r/w gptmcfg 0x000 170 gptm t imera mode 0x0000.0000 r/w gptmt amr 0x004 172 gptm t imerb mode 0x0000.0000 r/w gptmtbmr 0x008 167 october 01, 2007 preliminary lm3s600 microcontroller
see page description reset t ype name offset 174 gptm control 0x0000.0000 r/w gptmctl 0x00c 177 gptm interrupt mask 0x0000.0000 r/w gptmimr 0x018 179 gptm raw interrupt status 0x0000.0000 ro gptmris 0x01c 180 gptm masked interrupt status 0x0000.0000 ro gptmmis 0x020 181 gptm interrupt clear 0x0000.0000 w1c gptmicr 0x024 183 gptm t imera interval load 0x0000.ffff (16-bit mode) 0xffff .ffff (32-bit mode) r/w gptmt ailr 0x028 184 gptm t imerb interval load 0x0000.ffff r/w gptmtbilr 0x02c 185 gptm t imera match 0x0000.ffff (16-bit mode) 0xffff .ffff (32-bit mode) r/w gptmt ama tchr 0x030 186 gptm t imerb match 0x0000.ffff r/w gptmtbma tchr 0x034 187 gptm t imera prescale 0x0000.0000 r/w gptmt apr 0x038 188 gptm t imerb prescale 0x0000.0000 r/w gptmtbpr 0x03c 189 gptm t imera prescale match 0x0000.0000 r/w gptmt apmr 0x040 190 gptm t imerb prescale match 0x0000.0000 r/w gptmtbpmr 0x044 191 gptm t imera 0x0000.ffff (16-bit mode) 0xffff .ffff (32-bit mode) ro gptmt ar 0x048 192 gptm t imerb 0x0000.ffff ro gptmtbr 0x04c 9.5 register descriptions the remainder of this section lists and describes the gptm registers, in numerical order by address of fset. october 01, 2007 168 preliminary general-purpose t imers
register 1: gptm configuration (gptmcfg), offset 0x000 this register configures the global operation of the gptm module. the value written to this register determines whether the gptm is in 32- or 16-bit mode. gptm configuration (gptmcfg) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 of fset 0x000 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 gptmcfg reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:3 gptm configuration the gptmcfg values are defined as follows: description v alue 32-bit timer configuration. 0x0 32-bit real-time clock (r tc) counter configuration. 0x1 reserved. 0x2 reserved. 0x3 16-bit timer configuration, function is controlled by bits 1:0 of gptmt amr and gptmtbmr . 0x4-0x7 0x0 r/w gptmcfg 2:0 169 october 01, 2007 preliminary lm3s600 microcontroller
register 2: gptm t imera mode (gptmt amr), offset 0x004 this register configures the gptm based on the configuration selected in the gptmcfg register . when in 16-bit pwm mode, set the taams bit to 0x1, the tacmr bit to 0x0, and the tamr field to 0x2. gptm t imera mode (gptmt amr) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 of fset 0x004 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 t amr t acmr t aams reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:4 gptm t imera alternate mode select the taams values are defined as follows: description v alue capture mode is enabled. 0 pwm mode is enabled. 1 note: t o enable pwm mode, you must also clear the tacmr bit and set the tamr field to 0x2. 0 r/w t aams 3 gptm t imera capture mode the tacmr values are defined as follows: description v alue edge-count mode. 0 edge-t ime mode. 1 0 r/w t acmr 2 october 01, 2007 170 preliminary general-purpose t imers
description reset t ype name bit/field gptm t imera mode the tamr values are defined as follows: description v alue reserved. 0x0 one-shot t imer mode. 0x1 periodic t imer mode. 0x2 capture mode. 0x3 the t imer mode is based on the timer configuration defined by bits 2:0 in the gptmcfg register (16-or 32-bit). in 16-bit timer configuration, tamr controls the 16-bit timer modes for t imera. in 32-bit timer configuration, this register controls the mode and the contents of gptmtbmr are ignored. 0x0 r/w t amr 1:0 171 october 01, 2007 preliminary lm3s600 microcontroller
register 3: gptm t imerb mode (gptmtbmr), offset 0x008 this register configures the gptm based on the configuration selected in the gptmcfg register . when in 16-bit pwm mode, set the tbams bit to 0x1, the tbcmr bit to 0x0, and the tbmr field to 0x2. gptm t imerb mode (gptmtbmr) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 of fset 0x008 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 tbmr tbcmr tbams reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:4 gptm t imerb alternate mode select the tbams values are defined as follows: description v alue capture mode is enabled. 0 pwm mode is enabled. 1 note: t o enable pwm mode, you must also clear the tbcmr bit and set the tbmr field to 0x2. 0 r/w tbams 3 gptm t imerb capture mode the tbcmr values are defined as follows: description v alue edge-count mode. 0 edge-t ime mode. 1 0 r/w tbcmr 2 october 01, 2007 172 preliminary general-purpose t imers
description reset t ype name bit/field gptm t imerb mode the tbmr values are defined as follows: description v alue reserved. 0x0 one-shot t imer mode. 0x1 periodic t imer mode. 0x2 capture mode. 0x3 the timer mode is based on the timer configuration defined by bits 2:0 in the gptmcfg register . in 16-bit timer configuration, these bits control the 16-bit timer modes for t imerb. in 32-bit timer configuration, this register s contents are ignored and gptmt amr is used. 0x0 r/w tbmr 1:0 173 october 01, 2007 preliminary lm3s600 microcontroller
register 4: gptm control (gptmctl), offset 0x00c this register is used alongside the gptmcfg and gmtmtnmr registers to fine-tune the timer configuration, and to enable other features such as timer stall and the output trigger . gptm control (gptmctl) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 of fset 0x00c t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 t aen t ast all t aevent r tcen t aote t apwml reserved tben tbst all tbevent reserved tbote tbpwml reserved r/w r/w r/w r/w r/w r/w r/w ro r/w r/w r/w r/w ro r/w r/w ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:15 gptm t imerb pwm output level the tbpwml values are defined as follows: description v alue output is unaf fected. 0 output is inverted. 1 0 r/w tbpwml 14 gptm t imerb output t rigger enable the tbote values are defined as follows: description v alue the output t imerb trigger is disabled. 0 the output t imerb trigger is enabled. 1 0 r/w tbote 13 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 12 gptm t imerb event mode the tbevent values are defined as follows: description v alue positive edge. 0x0 negative edge. 0x1 reserved 0x2 both edges. 0x3 0x0 r/w tbevent 1 1:10 october 01, 2007 174 preliminary general-purpose t imers
description reset t ype name bit/field gptm t imerb stall enable the tbstall values are defined as follows: description v alue t imerb stalling is disabled. 0 t imerb stalling is enabled. 1 0 r/w tbst all 9 gptm t imerb enable the tben values are defined as follows: description v alue t imerb is disabled. 0 t imerb is enabled and begins counting or the capture logic is enabled based on the gptmcfg register . 1 0 r/w tben 8 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7 gptm t imera pwm output level the tapwml values are defined as follows: description v alue output is unaf fected. 0 output is inverted. 1 0 r/w t apwml 6 gptm t imera output t rigger enable the taote values are defined as follows: description v alue the output t imera trigger is disabled. 0 the output t imera trigger is enabled. 1 0 r/w t aote 5 gptm r tc enable the rtcen values are defined as follows: description v alue r tc counting is disabled. 0 r tc counting is enabled. 1 0 r/w r tcen 4 175 october 01, 2007 preliminary lm3s600 microcontroller
description reset t ype name bit/field gptm t imera event mode the taevent values are defined as follows: description v alue positive edge. 0x0 negative edge. 0x1 reserved 0x2 both edges. 0x3 0x0 r/w t aevent 3:2 gptm t imera stall enable the tastall values are defined as follows: description v alue t imera stalling is disabled. 0 t imera stalling is enabled. 1 0 r/w t ast all 1 gptm t imera enable the taen values are defined as follows: description v alue t imera is disabled. 0 t imera is enabled and begins counting or the capture logic is enabled based on the gptmcfg register . 1 0 r/w t aen 0 october 01, 2007 176 preliminary general-purpose t imers
register 5: gptm interrupt mask (gptmimr), offset 0x018 this register allows software to enable/disable gptm controller-level interrupts. w riting a 1 enables the interrupt, while writing a 0 disables it. gptm interrupt mask (gptmimr) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 of fset 0x018 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 t a t oim camim caeim r tcim reserved tbt oim cbmim cbeim reserved r/w r/w r/w r/w ro ro ro ro r/w r/w r/w ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 1 gptm captureb event interrupt mask the cbeim values are defined as follows: description v alue interrupt is disabled. 0 interrupt is enabled. 1 0 r/w cbeim 10 gptm captureb match interrupt mask the cbmim values are defined as follows: description v alue interrupt is disabled. 0 interrupt is enabled. 1 0 r/w cbmim 9 gptm t imerb t ime-out interrupt mask the tbtoim values are defined as follows: description v alue interrupt is disabled. 0 interrupt is enabled. 1 0 r/w tbt oim 8 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7:4 177 october 01, 2007 preliminary lm3s600 microcontroller
description reset t ype name bit/field gptm r tc interrupt mask the rtcim values are defined as follows: description v alue interrupt is disabled. 0 interrupt is enabled. 1 0 r/w r tcim 3 gptm capturea event interrupt mask the caeim values are defined as follows: description v alue interrupt is disabled. 0 interrupt is enabled. 1 0 r/w caeim 2 gptm capturea match interrupt mask the camim values are defined as follows: description v alue interrupt is disabled. 0 interrupt is enabled. 1 0 r/w camim 1 gptm t imera t ime-out interrupt mask the tatoim values are defined as follows: description v alue interrupt is disabled. 0 interrupt is enabled. 1 0 r/w t a t oim 0 october 01, 2007 178 preliminary general-purpose t imers
register 6: gptm raw interrupt status (gptmris), offset 0x01c this register shows the state of the gptm's internal interrupt signal. these bits are set whether or not the interrupt is masked in the gptmimr register . each bit can be cleared by writing a 1 to its corresponding bit in gptmicr . gptm raw interrupt status (gptmris) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 of fset 0x01c t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 t a t oris camris caeris r tcris reserved tbt oris cbmris cberis reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 1 gptm captureb event raw interrupt this is the captureb event interrupt status prior to masking. 0 ro cberis 10 gptm captureb match raw interrupt this is the captureb match interrupt status prior to masking. 0 ro cbmris 9 gptm t imerb t ime-out raw interrupt this is the t imerb time-out interrupt status prior to masking. 0 ro tbt oris 8 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:4 gptm r tc raw interrupt this is the r tc event interrupt status prior to masking. 0 ro r tcris 3 gptm capturea event raw interrupt this is the capturea event interrupt status prior to masking. 0 ro caeris 2 gptm capturea match raw interrupt this is the capturea match interrupt status prior to masking. 0 ro camris 1 gptm t imera t ime-out raw interrupt this the t imera time-out interrupt status prior to masking. 0 ro t a t oris 0 179 october 01, 2007 preliminary lm3s600 microcontroller
register 7: gptm masked interrupt status (gptmmis), offset 0x020 this register show the state of the gptm's controller-level interrupt. if an interrupt is unmasked in gptmimr , and there is an event that causes the interrupt to be asserted, the corresponding bit is set in this register . all bits are cleared by writing a 1 to the corresponding bit in gptmicr . gptm masked interrupt status (gptmmis) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 of fset 0x020 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 t a t omis cammis caemis r tcmis reserved tbt omis cbmmis cbemis reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 1 gptm captureb event masked interrupt this is the captureb event interrupt status after masking. 0 ro cbemis 10 gptm captureb match masked interrupt this is the captureb match interrupt status after masking. 0 ro cbmmis 9 gptm t imerb t ime-out masked interrupt this is the t imerb time-out interrupt status after masking. 0 ro tbt omis 8 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:4 gptm r tc masked interrupt this is the r tc event interrupt status after masking. 0 ro r tcmis 3 gptm capturea event masked interrupt this is the capturea event interrupt status after masking. 0 ro caemis 2 gptm capturea match masked interrupt this is the capturea match interrupt status after masking. 0 ro cammis 1 gptm t imera t ime-out masked interrupt this is the t imera time-out interrupt status after masking. 0 ro t a t omis 0 october 01, 2007 180 preliminary general-purpose t imers
register 8: gptm interrupt clear (gptmicr), offset 0x024 this register is used to clear the status bits in the gptmris and gptmmis registers. w riting a 1 to a bit clears the corresponding bit in the gptmris and gptmmis registers. gptm interrupt clear (gptmicr) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 of fset 0x024 t ype w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 t a t ocint camcint caecint r tccint reserved tbt ocint cbmcint cbecint reserved w1c w1c w1c w1c ro ro ro ro w1c w1c w1c ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 1 gptm captureb event interrupt clear the cbecint values are defined as follows: description v alue the interrupt is unaf fected. 0 the interrupt is cleared. 1 0 w1c cbecint 10 gptm captureb match interrupt clear the cbmcint values are defined as follows: description v alue the interrupt is unaf fected. 0 the interrupt is cleared. 1 0 w1c cbmcint 9 gptm t imerb t ime-out interrupt clear the tbtocint values are defined as follows: description v alue the interrupt is unaf fected. 0 the interrupt is cleared. 1 0 w1c tbt ocint 8 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:4 181 october 01, 2007 preliminary lm3s600 microcontroller
description reset t ype name bit/field gptm r tc interrupt clear the rtccint values are defined as follows: description v alue the interrupt is unaf fected. 0 the interrupt is cleared. 1 0 w1c r tccint 3 gptm capturea event interrupt clear the caecint values are defined as follows: description v alue the interrupt is unaf fected. 0 the interrupt is cleared. 1 0 w1c caecint 2 gptm capturea match raw interrupt this is the capturea match interrupt status after masking. 0 w1c camcint 1 gptm t imera t ime-out raw interrupt the tatocint values are defined as follows: description v alue the interrupt is unaf fected. 0 the interrupt is cleared. 1 0 w1c t a t ocint 0 october 01, 2007 182 preliminary general-purpose t imers
register 9: gptm t imera interval load (gptmt ailr), offset 0x028 this register is used to load the starting count value into the timer . when gptm is configured to one of the 32-bit modes, gptmt ailr appears as a 32-bit register (the upper 16-bits correspond to the contents of the gptm t imerb interval load (gptmtbilr) register). in 16-bit mode, the upper 16 bits of this register read as 0s and have no ef fect on the state of gptmtbilr . gptm t imera interval load (gptmt ailr) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 of fset 0x028 t ype r/w , reset 0x0000.ffff (16-bit mode) and 0xffff .ffff (32-bit mode) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 t ailrh r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 1 1 1 1 0 1 1 1 1 0 1 0 1 1 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 t ailrl r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset t ype name bit/field gptm t imera interval load register high when configured for 32-bit mode via the gptmcfg register , the gptm t imerb interval load (gptmtbilr) register loads this value on a write. a read returns the current value of gptmtbilr . in 16-bit mode, this field reads as 0 and does not have an ef fect on the state of gptmtbilr . 0xffff (32-bit mode) 0x0000 (16-bit mode) r/w t ailrh 31:16 gptm t imera interval load register low for both 16- and 32-bit modes, writing this field loads the counter for t imera. a read returns the current value of gptmt ailr . 0xffff r/w t ailrl 15:0 183 october 01, 2007 preliminary lm3s600 microcontroller
register 10: gptm t imerb interval load (gptmtbilr), offset 0x02c this register is used to load the starting count value into t imerb. when the gptm is configured to a 32-bit mode, gptmtbilr returns the current value of t imerb and ignores writes. gptm t imerb interval load (gptmtbilr) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 of fset 0x02c t ype r/w , reset 0x0000.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 tbilrl r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 gptm t imerb interval load register when the gptm is not configured as a 32-bit timer , a write to this field updates gptmtbilr . in 32-bit mode, writes are ignored, and reads return the current value of gptmtbilr . 0xffff r/w tbilrl 15:0 october 01, 2007 184 preliminary general-purpose t imers
register 1 1: gptm t imera match (gptmt ama tchr), offset 0x030 this register is used in 32-bit real-t ime clock mode and 16-bit pwm and input edge count modes. gptm t imera match (gptmt ama tchr) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 of fset 0x030 t ype r/w , reset 0x0000.ffff (16-bit mode) and 0xffff .ffff (32-bit mode) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 t amrh r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 1 1 1 1 0 1 1 1 1 0 1 0 1 1 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 t amrl r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset t ype name bit/field gptm t imera match register high when configured for 32-bit real-t ime clock (r tc) mode via the gptmcfg register , this value is compared to the upper half of gptmt ar , to determine match events. in 16-bit mode, this field reads as 0 and does not have an ef fect on the state of gptmtbma tchr . 0xffff (32-bit mode) 0x0000 (16-bit mode) r/w t amrh 31:16 gptm t imera match register low when configured for 32-bit real-t ime clock (r tc) mode via the gptmcfg register , this value is compared to the lower half of gptmt ar , to determine match events. when configured for pwm mode, this value along with gptmt ailr , determines the duty cycle of the output pwm signal. when configured for edge count mode, this value along with gptmt ailr , determines how many edge events are counted. the total number of edge events counted is equal to the value in gptmt ailr minus this value. 0xffff r/w t amrl 15:0 185 october 01, 2007 preliminary lm3s600 microcontroller
register 12: gptm t imerb match (gptmtbma tchr), offset 0x034 this register is used in 32-bit real-t ime clock mode and 16-bit pwm and input edge count modes. gptm t imerb match (gptmtbma tchr) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 of fset 0x034 t ype r/w , reset 0x0000.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 tbmrl r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 gptm t imerb match register low when configured for pwm mode, this value along with gptmtbilr , determines the duty cycle of the output pwm signal. when configured for edge count mode, this value along with gptmtbilr , determines how many edge events are counted. the total number of edge events counted is equal to the value in gptmtbilr minus this value. 0xffff r/w tbmrl 15:0 october 01, 2007 186 preliminary general-purpose t imers
register 13: gptm t imera prescale (gptmt apr), offset 0x038 this register allows software to extend the range of the 16-bit timers when operating in one-shot or periodic mode. gptm t imera prescale (gptmt apr) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 of fset 0x038 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 t apsr reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gptm t imera prescale the register loads this value on a write. a read returns the current value of the register . refer to t able 9-1 on page 161 for more details and an example. 0x00 r/w t apsr 7:0 187 october 01, 2007 preliminary lm3s600 microcontroller
register 14: gptm t imerb prescale (gptmtbpr), offset 0x03c this register allows software to extend the range of the 16-bit timers when operating in one-shot or periodic mode. gptm t imerb prescale (gptmtbpr) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 of fset 0x03c t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 tbpsr reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gptm t imerb prescale the register loads this value on a write. a read returns the current value of this register . refer to t able 9-1 on page 161 for more details and an example. 0x00 r/w tbpsr 7:0 october 01, 2007 188 preliminary general-purpose t imers
register 15: gptm t imera prescale match (gptmt apmr), offset 0x040 this register ef fectively extends the range of gptmt ama tchr to 24 bits when operating in 16-bit one-shot or periodic mode. gptm t imera prescale match (gptmt apmr) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 of fset 0x040 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 t apsmr reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gptm t imera prescale match this value is used alongside gptmt ama tchr to detect timer match events while using a prescaler . 0x00 r/w t apsmr 7:0 189 october 01, 2007 preliminary lm3s600 microcontroller
register 16: gptm t imerb prescale match (gptmtbpmr), offset 0x044 this register ef fectively extends the range of gptmtbma tchr to 24 bits when operating in 16-bit one-shot or periodic mode. gptm t imerb prescale match (gptmtbpmr) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 of fset 0x044 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 tbpsmr reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gptm t imerb prescale match this value is used alongside gptmtbma tchr to detect timer match events while using a prescaler . 0x00 r/w tbpsmr 7:0 october 01, 2007 190 preliminary general-purpose t imers
register 17: gptm t imera (gptmt ar), offset 0x048 this register shows the current value of the t imera counter in all cases except for input edge count mode. when in this mode, this register contains the time at which the last edge event took place. gptm t imera (gptmt ar) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 of fset 0x048 t ype ro, reset 0x0000.ffff (16-bit mode) and 0xffff .ffff (32-bit mode) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 t arh ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 1 1 1 1 0 1 1 1 1 0 1 0 1 1 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 t arl ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset t ype name bit/field gptm t imera register high if the gptmcfg is in a 32-bit mode, t imerb value is read. if the gptmcfg is in a 16-bit mode, this is read as zero. 0xffff (32-bit mode) 0x0000 (16-bit mode) ro t arh 31:16 gptm t imera register low a read returns the current value of the gptm t imera count register , except in input edge count mode, when it returns the timestamp from the last edge event. 0xffff ro t arl 15:0 191 october 01, 2007 preliminary lm3s600 microcontroller
register 18: gptm t imerb (gptmtbr), offset 0x04c this register shows the current value of the t imerb counter in all cases except for input edge count mode. when in this mode, this register contains the time at which the last edge event took place. gptm t imerb (gptmtbr) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 of fset 0x04c t ype ro, reset 0x0000.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 tbrl ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 gptm t imerb a read returns the current value of the gptm t imerb count register , except in input edge count mode, when it returns the timestamp from the last edge event. 0xffff ro tbrl 15:0 october 01, 2007 192 preliminary general-purpose t imers
10 w atchdog t imer a watchdog timer can generate nonmaskable interrupts (nmis) or a reset when a time-out value is reached. the watchdog timer is used to regain control when a system has failed due to a software error or due to the failure of an external device to respond in the expected way . the stellaris ? w atchdog t imer module consists of a 32-bit down counter , a programmable load register , interrupt generation logic, a locking register , and user-enabled stalling. the w atchdog t imer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. once the w atchdog t imer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. 10.1 block diagram figure 10-1. wdt module block diagram 10.2 functional description the w atchdog t imer module generates the first time-out signal when the 32-bit counter reaches the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt. after the first time-out event, the 32-bit counter is re-loaded with the value of the w atchdog t imer load (wdtload) register , and the timer resumes counting down from that value. once the 193 october 01, 2007 preliminary lm3s600 microcontroller control / clock / interrupt generation wdtctl wdticr wdtris wdtmis wdtlock wdttest wdtload wdtv alue comparator 32-bit down counter 0x00000000 interrupt system clock identification registers wdtpcellid 0 wdtperiphid 0 wdtperiphid 4 wdtpcellid 1 wdtperiphid 1 wdtperiphid 5 wdtpcellid 2 wdtperiphid 2 wdtperiphid 6 wdtpcellid 3 wdtperiphid 3 wdtperiphid 7
w atchdog t imer has been configured, the w atchdog t imer lock (wdtlock) register is written, which prevents the timer configuration from being inadvertently altered by software. if the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled (via the watchdogresetenable function), the w atchdog timer asserts its reset signal to the system. if the interrupt is cleared before the 32-bit counter reaches its second time-out, the 32-bit counter is loaded with the value in the wdtload register , and counting resumes from that value. if wdtload is written with a new value while the w atchdog t imer counter is counting, then the counter is loaded with the new value and continues counting. w riting to wdtload does not clear an active interrupt. an interrupt must be specifically cleared by writing to the w atchdog interrupt clear (wdticr) register . the w atchdog module interrupt and reset generation can be enabled or disabled as required. when the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its last state. 10.3 initialization and configuration t o use the wdt , its peripheral clock must be enabled by setting the wdt bit in the rcgc0 register . the w atchdog t imer is configured using the following sequence: 1. load the wdtload register with the desired timer load value. 2. if the w atchdog is configured to trigger system resets, set the resen bit in the wdtctl register . 3. set the inten bit in the wdtctl register to enable the w atchdog and lock the control register . if software requires that all of the watchdog registers are locked, the w atchdog t imer module can be fully locked by writing any value to the wdtlock register . t o unlock the w atchdog t imer , write a value of 0x1acc.e551. 10.4 register map t able 10-1 on page 194 lists the w atchdog registers. the of fset listed is a hexadecimal increment to the register s address, relative to the w atchdog t imer base address of 0x4000.0000. t able 10-1. w atchdog t imer register map see page description reset t ype name offset 196 w atchdog load 0xffff .ffff r/w wdtload 0x000 197 w atchdog v alue 0xffff .ffff ro wdtv alue 0x004 198 w atchdog control 0x0000.0000 r/w wdtctl 0x008 199 w atchdog interrupt clear - wo wdticr 0x00c 200 w atchdog raw interrupt status 0x0000.0000 ro wdtris 0x010 201 w atchdog masked interrupt status 0x0000.0000 ro wdtmis 0x014 202 w atchdog t est 0x0000.0000 r/w wdttest 0x418 203 w atchdog lock 0x0000.0000 r/w wdtlock 0xc00 october 01, 2007 194 preliminary w atchdog t imer
see page description reset t ype name offset 204 w atchdog peripheral identification 4 0x0000.0000 ro wdtperiphid4 0xfd0 205 w atchdog peripheral identification 5 0x0000.0000 ro wdtperiphid5 0xfd4 206 w atchdog peripheral identification 6 0x0000.0000 ro wdtperiphid6 0xfd8 207 w atchdog peripheral identification 7 0x0000.0000 ro wdtperiphid7 0xfdc 208 w atchdog peripheral identification 0 0x0000.0005 ro wdtperiphid0 0xfe0 209 w atchdog peripheral identification 1 0x0000.0018 ro wdtperiphid1 0xfe4 210 w atchdog peripheral identification 2 0x0000.0018 ro wdtperiphid2 0xfe8 211 w atchdog peripheral identification 3 0x0000.0001 ro wdtperiphid3 0xfec 212 w atchdog primecell identification 0 0x0000.000d ro wdtpcellid0 0xff0 213 w atchdog primecell identification 1 0x0000.00f0 ro wdtpcellid1 0xff4 214 w atchdog primecell identification 2 0x0000.0005 ro wdtpcellid2 0xff8 215 w atchdog primecell identification 3 0x0000.00b1 ro wdtpcellid3 0xffc 10.5 register descriptions the remainder of this section lists and describes the wdt registers, in numerical order by address of fset. 195 october 01, 2007 preliminary lm3s600 microcontroller
register 1: w atchdog load (wdtload), offset 0x000 this register is the 32-bit interval value used by the 32-bit counter . when this register is written, the value is immediately loaded and the counter restarts counting down from the new value. if the wdtload register is loaded with 0x0000.0000, an interrupt is immediately generated. w atchdog load (wdtload) base 0x4000.0000 of fset 0x000 t ype r/w , reset 0xffff .ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 wdtload r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 wdtload r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset t ype name bit/field w atchdog load v alue 0xffff .ffff r/w wdtload 31:0 october 01, 2007 196 preliminary w atchdog t imer
register 2: w atchdog v alue (wdtv alue), offset 0x004 this register contains the current count value of the timer . w atchdog v alue (wdtv alue) base 0x4000.0000 of fset 0x004 t ype ro, reset 0xffff .ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 wdtv alue ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 wdtv alue ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset t ype name bit/field w atchdog v alue current value of the 32-bit down counter . 0xffff .ffff ro wdtv alue 31:0 197 october 01, 2007 preliminary lm3s600 microcontroller
register 3: w atchdog control (wdtctl), offset 0x008 this register is the watchdog control register . the watchdog timer can be configured to generate a reset signal (on second time-out) or an interrupt on time-out. when the watchdog interrupt has been enabled, all subsequent writes to the control register are ignored. the only mechanism that can re-enable writes is a hardware reset. w atchdog control (wdtctl) base 0x4000.0000 of fset 0x008 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 inten resen reserved r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:2 w atchdog reset enable the resen values are defined as follows: description v alue disabled. 0 enable the w atchdog module reset output. 1 0 r/w resen 1 w atchdog interrupt enable the inten values are defined as follows: description v alue interrupt event disabled (once this bit is set, it can only be cleared by a hardware reset). 0 interrupt event enabled. once enabled, all writes are ignored. 1 0 r/w inten 0 october 01, 2007 198 preliminary w atchdog t imer
register 4: w atchdog interrupt clear (wdticr), offset 0x00c this register is the interrupt clear register . a write of any value to this register clears the w atchdog interrupt and reloads the 32-bit counter from the wdtload register . v alue for a read or reset is indeterminate. w atchdog interrupt clear (wdticr) base 0x4000.0000 of fset 0x00c t ype wo, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 wdtintclr wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo t ype - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 wdtintclr wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo t ype - - - - - - - - - - - - - - - - reset description reset t ype name bit/field w atchdog interrupt clear - wo wdtintclr 31:0 199 october 01, 2007 preliminary lm3s600 microcontroller
register 5: w atchdog raw interrupt status (wdtris), offset 0x010 this register is the raw interrupt status register . w atchdog interrupt events can be monitored via this register if the controller interrupt is masked. w atchdog raw interrupt status (wdtris) base 0x4000.0000 of fset 0x010 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 wdtris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 w atchdog raw interrupt status gives the raw interrupt state (prior to masking) of wdtintr . 0 ro wdtris 0 october 01, 2007 200 preliminary w atchdog t imer
register 6: w atchdog masked interrupt status (wdtmis), offset 0x014 this register is the masked interrupt status register . the value of this register is the logical and of the raw interrupt bit and the w atchdog interrupt enable bit. w atchdog masked interrupt status (wdtmis) base 0x4000.0000 of fset 0x014 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 wdtmis reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 w atchdog masked interrupt status gives the masked interrupt state (after masking) of the wdtintr interrupt. 0 ro wdtmis 0 201 october 01, 2007 preliminary lm3s600 microcontroller
register 7: w atchdog t est (wdttest), offset 0x418 this register provides user-enabled stalling when the microcontroller asserts the cpu halt flag during debug. w atchdog t est (wdttest) base 0x4000.0000 of fset 0x418 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved st all reserved ro ro ro ro ro ro ro ro r/w ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:9 w atchdog stall enable when set to 1, if the stellaris ? microcontroller is stopped with a debugger , the watchdog timer stops counting. once the microcontroller is restarted, the watchdog timer resumes counting. 0 r/w st all 8 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 7:0 october 01, 2007 202 preliminary w atchdog t imer
register 8: w atchdog lock (wdtlock), offset 0xc00 w riting 0x1acc.e551 to the wdtlock register enables write access to all other registers. w riting any other value to the wdtlock register re-enables the locked state for register writes to all the other registers. reading the wdtlock register returns the lock status rather than the 32-bit value written. therefore, when write accesses are disabled, reading the wdtlock register returns 0x0000.0001 (when locked; otherwise, the returned value is 0x0000.0000 (unlocked)). w atchdog lock (wdtlock) base 0x4000.0000 of fset 0xc00 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 wdtlock r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 wdtlock r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field w atchdog lock a write of the value 0x1acc.e551 unlocks the watchdog registers for write access. a write of any other value reapplies the lock, preventing any register updates. a read of this register returns the following values: description v alue locked 0x0000.0001 unlocked 0x0000.0000 0x0000 r/w wdtlock 31:0 203 october 01, 2007 preliminary lm3s600 microcontroller
register 9: w atchdog peripheral identification 4 (wdtperiphid4), offset 0xfd0 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. w atchdog peripheral identification 4 (wdtperiphid4) base 0x4000.0000 of fset 0xfd0 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid4 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 wdt peripheral id register[7:0] 0x00 ro pid4 7:0 october 01, 2007 204 preliminary w atchdog t imer
register 10: w atchdog peripheral identification 5 (wdtperiphid5), offset 0xfd4 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. w atchdog peripheral identification 5 (wdtperiphid5) base 0x4000.0000 of fset 0xfd4 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid5 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 wdt peripheral id register[15:8] 0x00 ro pid5 7:0 205 october 01, 2007 preliminary lm3s600 microcontroller
register 1 1: w atchdog peripheral identification 6 (wdtperiphid6), offset 0xfd8 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. w atchdog peripheral identification 6 (wdtperiphid6) base 0x4000.0000 of fset 0xfd8 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid6 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 wdt peripheral id register[23:16] 0x00 ro pid6 7:0 october 01, 2007 206 preliminary w atchdog t imer
register 12: w atchdog peripheral identification 7 (wdtperiphid7), offset 0xfdc the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. w atchdog peripheral identification 7 (wdtperiphid7) base 0x4000.0000 of fset 0xfdc t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid7 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 wdt peripheral id register[31:24] 0x00 ro pid7 7:0 207 october 01, 2007 preliminary lm3s600 microcontroller
register 13: w atchdog peripheral identification 0 (wdtperiphid0), offset 0xfe0 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. w atchdog peripheral identification 0 (wdtperiphid0) base 0x4000.0000 of fset 0xfe0 t ype ro, reset 0x0000.0005 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 w atchdog peripheral id register[7:0] 0x05 ro pid0 7:0 october 01, 2007 208 preliminary w atchdog t imer
register 14: w atchdog peripheral identification 1 (wdtperiphid1), offset 0xfe4 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. w atchdog peripheral identification 1 (wdtperiphid1) base 0x4000.0000 of fset 0xfe4 t ype ro, reset 0x0000.0018 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 w atchdog peripheral id register[15:8] 0x18 ro pid1 7:0 209 october 01, 2007 preliminary lm3s600 microcontroller
register 15: w atchdog peripheral identification 2 (wdtperiphid2), offset 0xfe8 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. w atchdog peripheral identification 2 (wdtperiphid2) base 0x4000.0000 of fset 0xfe8 t ype ro, reset 0x0000.0018 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 w atchdog peripheral id register[23:16] 0x18 ro pid2 7:0 october 01, 2007 210 preliminary w atchdog t imer
register 16: w atchdog peripheral identification 3 (wdtperiphid3), offset 0xfec the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. w atchdog peripheral identification 3 (wdtperiphid3) base 0x4000.0000 of fset 0xfec t ype ro, reset 0x0000.0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 w atchdog peripheral id register[31:24] 0x01 ro pid3 7:0 21 1 october 01, 2007 preliminary lm3s600 microcontroller
register 17: w atchdog primecell identification 0 (wdtpcellid0), offset 0xff0 the wdtpcellidn registers are hard-coded and the fields within the register determine the reset value. w atchdog primecell identification 0 (wdtpcellid0) base 0x4000.0000 of fset 0xff0 t ype ro, reset 0x0000.000d 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 w atchdog primecell id register[7:0] 0x0d ro cid0 7:0 october 01, 2007 212 preliminary w atchdog t imer
register 18: w atchdog primecell identification 1 (wdtpcellid1), offset 0xff4 the wdtpcellidn registers are hard-coded and the fields within the register determine the reset value. w atchdog primecell identification 1 (wdtpcellid1) base 0x4000.0000 of fset 0xff4 t ype ro, reset 0x0000.00f0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 w atchdog primecell id register[15:8] 0xf0 ro cid1 7:0 213 october 01, 2007 preliminary lm3s600 microcontroller
register 19: w atchdog primecell identification 2 (wdtpcellid2), offset 0xff8 the wdtpcellidn registers are hard-coded and the fields within the register determine the reset value. w atchdog primecell identification 2 (wdtpcellid2) base 0x4000.0000 of fset 0xff8 t ype ro, reset 0x0000.0005 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 w atchdog primecell id register[23:16] 0x05 ro cid2 7:0 october 01, 2007 214 preliminary w atchdog t imer
register 20: w atchdog primecell identification 3 (wdtpcellid3 ), offset 0xffc the wdtpcellidn registers are hard-coded and the fields within the register determine the reset value. w atchdog primecell identification 3 (wdtpcellid3) base 0x4000.0000 of fset 0xffc t ype ro, reset 0x0000.00b1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 w atchdog primecell id register[31:24] 0xb1 ro cid3 7:0 215 october 01, 2007 preliminary lm3s600 microcontroller
1 1 universal asynchronous receivers/t ransmitters (uart s) the stellaris ? universal asynchronous receiver/t ransmitter (uar t) provides fully programmable, 16c550-type serial interface characteristics. the lm3s600 controller is equipped with two uar t modules. each uar t has the following features: separate transmit and receive fifos programmable fifo length, including 1-byte deep operation providing conventional double-buf fered interface fifo trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 programmable baud-rate generator allowing rates up to 3.125 mbps standard asynchronous communication bits for start, stop, and parity false start bit detection line-break generation and detection fully programmable serial interface characteristics: C 5, 6, 7, or 8 data bits C even, odd, stick, or no-parity bit generation/detection C 1 or 2 stop bit generation october 01, 2007 216 preliminary universal asynchronous receivers/t ransmitters (uar t s)
1 1.1 block diagram figure 1 1-1. uart module block diagram 1 1.2 functional description each stellaris ? uar t performs the functions of parallel-to-serial and serial-to-parallel conversions. it is similar in functionality to a 16c550 uar t , but is not register compatible. the uar t is configured for transmit and/or receive via the txe and rxe bits of the uart control (uartctl) register (see page 233 ). t ransmit and receive are both enabled out of reset. before any control registers are programmed, the uar t must be disabled by clearing the uarten bit in uartctl . if the uar t is disabled during a tx or rx operation, the current transaction is completed prior to the uar t stopping. 1 1.2.1 t ransmit/receive logic the transmit logic performs parallel-to-serial conversion on the data read from the transmit fifo. the control logic outputs the serial bit stream beginning with a start bit, and followed by the data bits (lsb first), parity bit, and the stop bits according to the programmed configuration in the control registers. see figure 1 1-2 on page 218 for details. 217 october 01, 2007 preliminary lm3s600 microcontroller receiver t ransmitter system clock control / status uar trsr / ecr uar tfr uar tlcrh uar tctl uar tilpr interrupt control uar tifls uar tim uar tmis uar tris uar ticr baud rate generator uar tibrd uar tfbrd identification registers uar tpcellid 0 uar tpcellid 1 uar tpcellid 2 uar tpcellid 3 uar tperiphid 0 uar tperiphid 1 uar tperiphid 2 uar tperiphid 3 uar t periphid 4 uar tperiphid 5 uar tperiphid 6 uar tperiphid 7 uar tdr txfifo 16 x 8 . . . rxfifo 16 x 8 . . . interrupt untx unrx
the receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse has been detected. overrun, parity , frame error checking, and line-break detection are also performed, and their status accompanies the data that is written to the receive fifo. figure 1 1-2. uart character frame 1 1.2.2 baud-rate generation the baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. the number formed by these two values is used by the baud-rate generator to determine the bit period. having a fractional baud-rate divider allows the uar t to generate all the standard baud rates. the 16-bit integer is loaded through the uart integer baud-rate divisor (uartibrd) register (see page 229 ) and the 6-bit fractional part is loaded with the uart fractional baud-rate divisor (uartfbrd) register (see page 230 ). the baud-rate divisor (brd) has the following relationship to the system clock (where brdi is the integer part of the brd and brdf is the fractional part, separated by a decimal place.): brd = brdi + brdf = sysclk / (16 * baud rate) the 6-bit fractional number (that is to be loaded into the divfrac bit field in the uartfbrd register) can be calculated by taking the fractional part of the baud-rate divisor , multiplying it by 64, and adding 0.5 to account for rounding errors: uartfbrd[divfrac] = integer(brdf * 64 + 0.5) the uar t generates an internal baud-rate reference clock at 16x the baud-rate (referred to as baud16 ). this reference clock is divided by 16 to generate the transmit clock, and is used for error detection during receive operations. along with the uart line control, high byte (uartlcrh) register (see page 231 ), the uartibrd and uartfbrd registers form an internal 30-bit register . this internal register is only updated when a write operation to uartlcrh is performed, so any changes to the baud-rate divisor must be followed by a write to the uartlcrh register for the changes to take ef fect. t o update the baud-rate registers, there are four possible sequences: uartibrd write, uartfbrd write, and uartlcrh write uartfbrd write, uartibrd write, and uartlcrh write uartibrd write and uartlcrh write uartfbrd write and uartlcrh write october 01, 2007 218 preliminary universal asynchronous receivers/t ransmitters (uar t s) 1 0 5 - 8 d a t a b i t s l s b m s b p a r i t y b i t i f e n a b l e d 1 - 2 s t o p b i t s u n t x n s t a r t
1 1.2.3 data t ransmission data received or transmitted is stored in two 16-byte fifos, though the receive fifo has an extra four bits per character for status information. for transmission, data is written into the transmit fifo. if the uar t is enabled, it causes a data frame to start transmitting with the parameters indicated in the uartlcrh register . data continues to be transmitted until there is no data left in the transmit fifo. the busy bit in the uart flag (uartfr) register (see page 227 ) is asserted as soon as data is written to the transmit fifo (that is, if the fifo is non-empty) and remains asserted while data is being transmitted. the busy bit is negated only when the transmit fifo is empty , and the last character has been transmitted from the shift register , including the stop bits. the uar t can indicate that it is busy even though the uar t may no longer be enabled. when the receiver is idle (the unrx is continuously 1) and the data input goes low (a start bit has been received), the receive counter begins running and data is sampled on the eighth cycle of baud16 (described in t ransmit/receive logic on page 217 ). the start bit is valid if unrx is still low on the eighth cycle of baud16 , otherwise a false start bit is detected and it is ignored. start bit errors can be viewed in the uart receive status (uartrsr) register (see page 225 ). if the start bit was valid, successive data bits are sampled on every 16th cycle of baud16 (that is, one bit period later) according to the programmed length of the data characters. the parity bit is then checked if parity mode was enabled. data length and parity are defined in the uartlcrh register . lastly , a valid stop bit is confirmed if unrx is high, otherwise a framing error has occurred. when a full word is received, the data is stored in the receive fifo, with any error bits associated with that word. 1 1.2.4 fifo operation the uar t has two 16-entry fifos; one for transmit and one for receive. both fifos are accessed via the uart data (uartdr) register (see page 223 ). read operations of the uartdr register return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data in the transmit fifo. out of reset, both fifos are disabled and act as 1-byte-deep holding registers. the fifos are enabled by setting the fen bit in uartlcrh ( page 231 ). fifo status can be monitored via the uart flag (uartfr) register (see page 227 ) and the uart receive status (uartrsr) register . hardware monitors empty , full and overrun conditions. the uartfr register contains empty and full flags ( txfe , txff , rxfe , and rxff bits) and the uartrsr register shows overrun status via the oe bit. the trigger points at which the fifos generate interrupts is controlled via the uart interrupt fifo level select (uartifls) register (see page 234 ). both fifos can be individually configured to trigger interrupts at dif ferent levels. a vailable configurations include 1/8, ?, ?, ?, and 7/8. for example, if the ? option is selected for the receive fifo, the uar t generates a receive interrupt after 4 data bytes are received. out of reset, both fifos are configured to trigger an interrupt at the ? mark. 1 1.2.5 interrupts the uar t can generate interrupts when the following conditions are observed: overrun error break error 219 october 01, 2007 preliminary lm3s600 microcontroller
parity error framing error receive t imeout t ransmit (when condition defined in the txiflsel bit in the uartifls register is met) receive (when condition defined in the rxiflsel bit in the uartifls register is met) all of the interrupt events are ored together before being sent to the interrupt controller , so the uar t can only generate a single interrupt request to the controller at any given time. software can service multiple interrupt events in a single interrupt service routine by reading the uart masked interrupt status (uartmis) register (see page 239 ). the interrupt events that can trigger a controller-level interrupt are defined in the uart interrupt mask (uartim ) register (see page 236 ) by setting the corresponding im bit to 1. if interrupts are not used, the raw interrupt status is always visible via the uart raw interrupt status (uartris) register (see page 238 ). interrupts are always cleared (for both the uartmis and uartris registers) by setting the corresponding bit in the uart interrupt clear (uarticr) register (see page 240 ). the receive timeout interrupt is asserted when the receive fifo is not empty , and no further data is received over a 32-bit period. the receive timeout interrupt is cleared either when the fifo becomes empty through reading all the data (or by reading the holding register), or when a 1 is written to the corresponding bit in the uarticr register . 1 1.2.6 loopback operation the uar t can be placed into an internal loopback mode for diagnostic or debug work. this is accomplished by setting the lbe bit in the uartctl register (see page 233 ). in loopback mode, data transmitted on untx is received on the unrx input. 1 1.3 initialization and configuration t o use the uar t s, the peripheral clock must be enabled by setting the uart0 or uart1 bits in the rcgc1 register . this section discusses the steps that are required for using a uar t module. for this example, the system clock is assumed to be 20 mhz and the desired uar t configuration is: 1 15200 baud rate data length of 8 bits one stop bit no parity fifos disabled no interrupts the first thing to consider when programming the uar t is the baud-rate divisor (brd), since the uartibrd and uartfbrd registers must be written before the uartlcrh register . using the equation described in baud-rate generation on page 218 , the brd can be calculated: october 01, 2007 220 preliminary universal asynchronous receivers/t ransmitters (uar t s)
brd = 20,000,000 / (16 * 115,200) = 10.8507 which means that the divint field of the uartibrd register (see page 229 ) should be set to 10. the value to be loaded into the uartfbrd register (see page 230 ) is calculated by the equation: uartfbrd[divfrac] = integer(0.8507 * 64 + 0.5) = 54 with the brd values in hand, the uar t configuration is written to the module in the following order: 1. disable the uar t by clearing the uarten bit in the uartctl register . 2. w rite the integer portion of the brd to the uartibrd register . 3. w rite the fractional portion of the brd to the uartfbrd register . 4. w rite the desired serial parameters to the uartlcrh register (in this case, a value of 0x0000.0060). 5. enable the uar t by setting the uarten bit in the uartctl register . 1 1.4 register map t able 1 1-1 on page 221 lists the uar t registers. the of fset listed is a hexadecimal increment to the register s address, relative to that uar t s base address: uar t0: 0x4000.c000 uar t1: 0x4000.d000 note: the uar t must be disabled (see the uarten bit in the uartctl register on page 233 ) before any of the control registers are reprogrammed. when the uar t is disabled during a tx or rx operation, the current transaction is completed prior to the uar t stopping. t able 1 1-1. uart register map see page description reset t ype name offset 223 uar t data 0x0000.0000 r/w uar tdr 0x000 225 uar t receive status/error clear 0x0000.0000 r/w uar trsr/uar tecr 0x004 227 uar t flag 0x0000.0090 ro uar tfr 0x018 229 uar t integer baud-rate divisor 0x0000.0000 r/w uar tibrd 0x024 230 uar t fractional baud-rate divisor 0x0000.0000 r/w uar tfbrd 0x028 231 uar t line control 0x0000.0000 r/w uar tlcrh 0x02c 233 uar t control 0x0000.0300 r/w uar tctl 0x030 234 uar t interrupt fifo level select 0x0000.0012 r/w uar tifls 0x034 236 uar t interrupt mask 0x0000.0000 r/w uar tim 0x038 238 uar t raw interrupt status 0x0000.000f ro uar tris 0x03c 239 uar t masked interrupt status 0x0000.0000 ro uar tmis 0x040 221 october 01, 2007 preliminary lm3s600 microcontroller
see page description reset t ype name offset 240 uar t interrupt clear 0x0000.0000 w1c uar ticr 0x044 242 uar t peripheral identification 4 0x0000.0000 ro uar tperiphid4 0xfd0 243 uar t peripheral identification 5 0x0000.0000 ro uar tperiphid5 0xfd4 244 uar t peripheral identification 6 0x0000.0000 ro uar tperiphid6 0xfd8 245 uar t peripheral identification 7 0x0000.0000 ro uar tperiphid7 0xfdc 246 uar t peripheral identification 0 0x0000.001 1 ro uar tperiphid0 0xfe0 247 uar t peripheral identification 1 0x0000.0000 ro uar tperiphid1 0xfe4 248 uar t peripheral identification 2 0x0000.0018 ro uar tperiphid2 0xfe8 249 uar t peripheral identification 3 0x0000.0001 ro uar tperiphid3 0xfec 250 uar t primecell identification 0 0x0000.000d ro uar tpcellid0 0xff0 251 uar t primecell identification 1 0x0000.00f0 ro uar tpcellid1 0xff4 252 uar t primecell identification 2 0x0000.0005 ro uar tpcellid2 0xff8 253 uar t primecell identification 3 0x0000.00b1 ro uar tpcellid3 0xffc 1 1.5 register descriptions the remainder of this section lists and describes the uar t registers, in numerical order by address of fset. october 01, 2007 222 preliminary universal asynchronous receivers/t ransmitters (uar t s)
register 1: uart data (uartdr), offset 0x000 this register is the data register (the interface to the fifos). when fifos are enabled, data written to this location is pushed onto the transmit fifo. if fifos are disabled, data is stored in the transmitter holding register (the bottom word of the transmit fifo). a write to this register initiates a transmission from the uar t . for received data, if the fifo is enabled, the data byte and the 4-bit status (break, frame, parity , and overrun) is pushed onto the 12-bit wide receive fifo. if fifos are disabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive fifo). the received data can be retrieved by reading this register . uar t data (uar tdr) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0x000 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 da t a fe pe be oe reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:12 uar t overrun error the oe values are defined as follows: description v alue there has been no data loss due to a fifo overrun. 0 new data was received when the fifo was full, resulting in data loss. 1 0 ro oe 1 1 uar t break error this bit is set to 1 when a break condition is detected, indicating that the receive data input was held low for longer than a full-word transmission time (defined as start, data, parity , and stop bits). in fifo mode, this error is associated with the character at the top of the fifo. when a break occurs, only one 0 character is loaded into the fifo. the next character is only enabled after the received data input goes to a 1 (marking state) and the next valid start bit is received. 0 ro be 10 223 october 01, 2007 preliminary lm3s600 microcontroller
description reset t ype name bit/field uar t parity error this bit is set to 1 when the parity of the received data character does not match the parity defined by bits 2 and 7 of the uartlcrh register . in fifo mode, this error is associated with the character at the top of the fifo. 0 ro pe 9 uar t framing error this bit is set to 1 when the received character does not have a valid stop bit (a valid stop bit is 1). 0 ro fe 8 data t ransmitted or received when written, the data that is to be transmitted via the uar t . when read, the data that was received by the uar t . 0 r/w da t a 7:0 october 01, 2007 224 preliminary universal asynchronous receivers/t ransmitters (uar t s)
register 2: uart receive status/error clear (uartrsr/uartecr), offset 0x004 the uartrsr/uartecr register is the receive status register/error clear register . in addition to the uartdr register , receive status can also be read from the uartrsr register . if the status is read from this register , then the status information corresponds to the entry read from uartdr prior to reading uartrsr . the status information for overrun is set immediately when an overrun condition occurs. a write of any value to the uartecr register clears the framing, parity , break, and overrun errors. all the bits are cleared to 0 on reset. read-only receive status (uartrsr) register uar t receive status/error clear (uar trsr/uar tecr) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0x004 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 fe pe be oe reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. the uartrsr register cannot be written. 0 ro reserved 31:4 uar t overrun error when this bit is set to 1, data is received and the fifo is already full. this bit is cleared to 0 by a write to uartecr . the fifo contents remain valid since no further data is written when the fifo is full, only the contents of the shift register are overwritten. the cpu must now read the data in order to empty the fifo. 0 ro oe 3 uar t break error this bit is set to 1 when a break condition is detected, indicating that the received data input was held low for longer than a full-word transmission time (defined as start, data, parity , and stop bits). this bit is cleared to 0 by a write to uartecr . in fifo mode, this error is associated with the character at the top of the fifo. when a break occurs, only one 0 character is loaded into the fifo. the next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. 0 ro be 2 225 october 01, 2007 preliminary lm3s600 microcontroller
description reset t ype name bit/field uar t parity error this bit is set to 1 when the parity of the received data character does not match the parity defined by bits 2 and 7 of the uartlcrh register . this bit is cleared to 0 by a write to uartecr . 0 ro pe 1 uar t framing error this bit is set to 1 when the received character does not have a valid stop bit (a valid stop bit is 1). this bit is cleared to 0 by a write to uartecr . in fifo mode, this error is associated with the character at the top of the fifo. 0 ro fe 0 w rite-only error clear (uartecr) register uar t receive status/error clear (uar trsr/uar tecr) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0x004 t ype wo, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 da t a reserved wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 wo reserved 31:8 error clear a write to this register of any data clears the framing, parity , break, and overrun flags. 0 wo da t a 7:0 october 01, 2007 226 preliminary universal asynchronous receivers/t ransmitters (uar t s)
register 3: uart flag (uartfr), offset 0x018 the uartfr register is the flag register . after reset, the txff , rxff , and busy bits are 0, and txfe and rxfe bits are 1. uar t flag (uar tfr) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0x018 t ype ro, reset 0x0000.0090 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved busy rxfe txff rxff txfe reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:8 uar t t ransmit fifo empty the meaning of this bit depends on the state of the fen bit in the uartlcrh register . if the fifo is disabled ( fen is 0), this bit is set when the transmit holding register is empty . if the fifo is enabled ( fen is 1), this bit is set when the transmit fifo is empty . 1 ro txfe 7 uar t receive fifo full the meaning of this bit depends on the state of the fen bit in the uartlcrh register . if the fifo is disabled, this bit is set when the receive holding register is full. if the fifo is enabled, this bit is set when the receive fifo is full. 0 ro rxff 6 uar t t ransmit fifo full the meaning of this bit depends on the state of the fen bit in the uartlcrh register . if the fifo is disabled, this bit is set when the transmit holding register is full. if the fifo is enabled, this bit is set when the transmit fifo is full. 0 ro txff 5 227 october 01, 2007 preliminary lm3s600 microcontroller
description reset t ype name bit/field uar t receive fifo empty the meaning of this bit depends on the state of the fen bit in the uartlcrh register . if the fifo is disabled, this bit is set when the receive holding register is empty . if the fifo is enabled, this bit is set when the receive fifo is empty . 1 ro rxfe 4 uar t busy when this bit is 1, the uar t is busy transmitting data. this bit remains set until the complete byte, including all stop bits, has been sent from the shift register . this bit is set as soon as the transmit fifo becomes non-empty (regardless of whether uar t is enabled). 0 ro busy 3 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 2:0 october 01, 2007 228 preliminary universal asynchronous receivers/t ransmitters (uar t s)
register 4: uart integer baud-rate divisor (uartibrd), offset 0x024 the uartibrd register is the integer part of the baud-rate divisor value. all the bits are cleared on reset. the minimum possible divide ratio is 1 (when uartibrd =0), in which case the uartfbrd register is ignored. when changing the uartibrd register , the new value does not take ef fect until transmission/reception of the current character is complete. any changes to the baud-rate divisor must be followed by a write to the uartlcrh register . see baud-rate generation on page 218 for configuration details. uar t integer baud-rate divisor (uar tibrd) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0x024 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 divint r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:16 integer baud-rate divisor 0x0000 r/w divint 15:0 229 october 01, 2007 preliminary lm3s600 microcontroller
register 5: uart fractional baud-rate divisor (uartfbrd), offset 0x028 the uartfbrd register is the fractional part of the baud-rate divisor value. all the bits are cleared on reset. when changing the uartfbrd register , the new value does not take ef fect until transmission/reception of the current character is complete. any changes to the baud-rate divisor must be followed by a write to the uartlcrh register . see baud-rate generation on page 218 for configuration details. uar t fractional baud-rate divisor (uar tfbrd) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0x028 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 divfrac reserved r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:6 fractional baud-rate divisor 0x000 r/w divfrac 5:0 october 01, 2007 230 preliminary universal asynchronous receivers/t ransmitters (uar t s)
register 6: uart line control (uartlcrh), offset 0x02c the uartlcrh register is the line control register . serial parameters such as data length, parity , and stop bit selection are implemented in this register . when updating the baud-rate divisor ( uartibrd and/or uartifrd ), the uartlcrh register must also be written. the write strobe for the baud-rate divisor registers is tied to the uartlcrh register . uar t line control (uar tlcrh) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0x02c t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 brk pen eps stp2 fen wlen sps reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:8 uar t stick parity select when bits 1, 2, and 7 of uartlcrh are set, the parity bit is transmitted and checked as a 0. when bits 1 and 7 are set and 2 is cleared, the parity bit is transmitted and checked as a 1. when this bit is cleared, stick parity is disabled. 0 r/w sps 7 uar t w ord length the bits indicate the number of data bits transmitted or received in a frame as follows: description v alue 8 bits 0x3 7 bits 0x2 6 bits 0x1 5 bits (default) 0x0 0 r/w wlen 6:5 uar t enable fifos if this bit is set to 1, transmit and receive fifo buf fers are enabled (fifo mode). when cleared to 0, fifos are disabled (character mode). the fifos become 1-byte-deep holding registers. 0 r/w fen 4 231 october 01, 2007 preliminary lm3s600 microcontroller
description reset t ype name bit/field uar t t wo stop bits select if this bit is set to 1, two stop bits are transmitted at the end of a frame. the receive logic does not check for two stop bits being received. 0 r/w stp2 3 uar t even parity select if this bit is set to 1, even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. when cleared to 0, then odd parity is performed, which checks for an odd number of 1s. this bit has no ef fect when parity is disabled by the pen bit. 0 r/w eps 2 uar t parity enable if this bit is set to 1, parity checking and generation is enabled; otherwise, parity is disabled and no parity bit is added to the data frame. 0 r/w pen 1 uar t send break if this bit is set to 1, a low level is continually output on the untx output, after completing transmission of the current character . for the proper execution of the break command, the software must set this bit for at least two frames (character periods). for normal use, this bit must be cleared to 0. 0 r/w brk 0 october 01, 2007 232 preliminary universal asynchronous receivers/t ransmitters (uar t s)
register 7: uart control (uartctl), offset 0x030 the uartctl register is the control register . all the bits are cleared on reset except for the transmit enable (txe) and receive enable (rxe) bits, which are set to 1. t o enable the uar t module, the uarten bit must be set to 1. if software requires a configuration change in the module, the uarten bit must be cleared before the configuration changes are written. if the uar t is disabled during a transmit or receive operation, the current transaction is completed prior to the uar t stopping. uar t control (uar tctl) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0x030 t ype r/w , reset 0x0000.0300 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 uar ten reserved lbe txe rxe reserved r/w ro ro ro ro ro ro r/w r/w r/w ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:10 uar t receive enable if this bit is set to 1, the receive section of the uar t is enabled. when the uar t is disabled in the middle of a receive, it completes the current character before stopping. note: t o enable reception, the uarten bit must also be set. 1 r/w rxe 9 uar t t ransmit enable if this bit is set to 1, the transmit section of the uar t is enabled. when the uar t is disabled in the middle of a transmission, it completes the current character before stopping. note: t o enable transmission, the uarten bit must also be set. 1 r/w txe 8 uar t loop back enable if this bit is set to 1, the untx path is fed through the unrx path. 0 r/w lbe 7 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 6:1 uar t enable if this bit is set to 1, the uar t is enabled. when the uar t is disabled in the middle of transmission or reception, it completes the current character before stopping. 0 r/w uar ten 0 233 october 01, 2007 preliminary lm3s600 microcontroller
register 8: uart interrupt fifo level select (uartifls), offset 0x034 the uartifls register is the interrupt fifo level select register . y ou can use this register to define the fifo level at which the txris and rxris bits in the uartris register are triggered. the interrupts are generated based on a transition through a level rather than being based on the level. that is, the interrupts are generated when the fill level progresses through the trigger level. for example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the module is receiving the 9th character . out of reset, the txiflsel and rxiflsel bits are configured so that the fifos trigger an interrupt at the half-way mark. uar t interrupt fifo level select (uar tifls) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0x034 t ype r/w , reset 0x0000.0012 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 txiflsel rxiflsel reserved r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro t ype 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:6 uar t receive interrupt fifo level select the trigger points for the receive interrupt are as follows: description v alue rx fifo 1/8 full 0x0 rx fifo ? full 0x1 rx fifo ? full (default) 0x2 rx fifo ? full 0x3 rx fifo 7/8 full 0x4 reserved 0x5-0x7 0x2 r/w rxiflsel 5:3 october 01, 2007 234 preliminary universal asynchronous receivers/t ransmitters (uar t s)
description reset t ype name bit/field uar t t ransmit interrupt fifo level select the trigger points for the transmit interrupt are as follows: description v alue tx fifo 1/8 full 0x0 tx fifo ? full 0x1 tx fifo ? full (default) 0x2 tx fifo ? full 0x3 tx fifo 7/8 full 0x4 reserved 0x5-0x7 0x2 r/w txiflsel 2:0 235 october 01, 2007 preliminary lm3s600 microcontroller
register 9: uart interrupt mask (uartim), offset 0x038 the uartim register is the interrupt mask set/clear register . on a read, this register gives the current value of the mask on the relevant interrupt. w riting a 1 to a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller . w riting a 0 prevents the raw interrupt signal from being sent to the interrupt controller . uar t interrupt mask (uar tim) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0x038 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved rxim txim r tim feim peim beim oeim reserved ro ro ro ro r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 1 uar t overrun error interrupt mask on a read, the current mask for the oeim interrupt is returned. setting this bit to 1 promotes the oeim interrupt to the interrupt controller . 0 r/w oeim 10 uar t break error interrupt mask on a read, the current mask for the beim interrupt is returned. setting this bit to 1 promotes the beim interrupt to the interrupt controller . 0 r/w beim 9 uar t parity error interrupt mask on a read, the current mask for the peim interrupt is returned. setting this bit to 1 promotes the peim interrupt to the interrupt controller . 0 r/w peim 8 uar t framing error interrupt mask on a read, the current mask for the feim interrupt is returned. setting this bit to 1 promotes the feim interrupt to the interrupt controller . 0 r/w feim 7 uar t receive t ime-out interrupt mask on a read, the current mask for the rtim interrupt is returned. setting this bit to 1 promotes the rtim interrupt to the interrupt controller . 0 r/w r tim 6 uar t t ransmit interrupt mask on a read, the current mask for the txim interrupt is returned. setting this bit to 1 promotes the txim interrupt to the interrupt controller . 0 r/w txim 5 october 01, 2007 236 preliminary universal asynchronous receivers/t ransmitters (uar t s)
description reset t ype name bit/field uar t receive interrupt mask on a read, the current mask for the rxim interrupt is returned. setting this bit to 1 promotes the rxim interrupt to the interrupt controller . 0 r/w rxim 4 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 3:0 237 october 01, 2007 preliminary lm3s600 microcontroller
register 10: uart raw interrupt status (uartris), offset 0x03c the uartris register is the raw interrupt status register . on a read, this register gives the current raw status value of the corresponding interrupt. a write has no ef fect. uar t raw interrupt status (uar tris) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0x03c t ype ro, reset 0x0000.000f 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved rxris txris r tris feris peris beris oeris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 1 uar t overrun error raw interrupt status gives the raw interrupt state (prior to masking) of this interrupt. 0 ro oeris 10 uar t break error raw interrupt status gives the raw interrupt state (prior to masking) of this interrupt. 0 ro beris 9 uar t parity error raw interrupt status gives the raw interrupt state (prior to masking) of this interrupt. 0 ro peris 8 uar t framing error raw interrupt status gives the raw interrupt state (prior to masking) of this interrupt. 0 ro feris 7 uar t receive t ime-out raw interrupt status gives the raw interrupt state (prior to masking) of this interrupt. 0 ro r tris 6 uar t t ransmit raw interrupt status gives the raw interrupt state (prior to masking) of this interrupt. 0 ro txris 5 uar t receive raw interrupt status gives the raw interrupt state (prior to masking) of this interrupt. 0 ro rxris 4 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0xf ro reserved 3:0 october 01, 2007 238 preliminary universal asynchronous receivers/t ransmitters (uar t s)
register 1 1: uart masked interrupt status (uartmis), offset 0x040 the uartmis register is the masked interrupt status register . on a read, this register gives the current masked status value of the corresponding interrupt. a write has no ef fect. uar t masked interrupt status (uar tmis) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0x040 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved rxmis txmis r tmis femis pemis bemis oemis reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 1 uar t overrun error masked interrupt status gives the masked interrupt state of this interrupt. 0 ro oemis 10 uar t break error masked interrupt status gives the masked interrupt state of this interrupt. 0 ro bemis 9 uar t parity error masked interrupt status gives the masked interrupt state of this interrupt. 0 ro pemis 8 uar t framing error masked interrupt status gives the masked interrupt state of this interrupt. 0 ro femis 7 uar t receive t ime-out masked interrupt status gives the masked interrupt state of this interrupt. 0 ro r tmis 6 uar t t ransmit masked interrupt status gives the masked interrupt state of this interrupt. 0 ro txmis 5 uar t receive masked interrupt status gives the masked interrupt state of this interrupt. 0 ro rxmis 4 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3:0 239 october 01, 2007 preliminary lm3s600 microcontroller
register 12: uart interrupt clear (uarticr), offset 0x044 the uarticr register is the interrupt clear register . on a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared. a write of 0 has no ef fect. uar t interrupt clear (uar ticr) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0x044 t ype w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved rxic txic r tic feic peic beic oeic reserved ro ro ro ro w1c w1c w1c w1c w1c w1c w1c ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 1 overrun error interrupt clear the oeic values are defined as follows: description v alue no ef fect on the interrupt. 0 clears interrupt. 1 0 w1c oeic 10 break error interrupt clear the beic values are defined as follows: description v alue no ef fect on the interrupt. 0 clears interrupt. 1 0 w1c beic 9 parity error interrupt clear the peic values are defined as follows: description v alue no ef fect on the interrupt. 0 clears interrupt. 1 0 w1c peic 8 october 01, 2007 240 preliminary universal asynchronous receivers/t ransmitters (uar t s)
description reset t ype name bit/field framing error interrupt clear the feic values are defined as follows: description v alue no ef fect on the interrupt. 0 clears interrupt. 1 0 w1c feic 7 receive t ime-out interrupt clear the rtic values are defined as follows: description v alue no ef fect on the interrupt. 0 clears interrupt. 1 0 w1c r tic 6 t ransmit interrupt clear the txic values are defined as follows: description v alue no ef fect on the interrupt. 0 clears interrupt. 1 0 w1c txic 5 receive interrupt clear the rxic values are defined as follows: description v alue no ef fect on the interrupt. 0 clears interrupt. 1 0 w1c rxic 4 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 3:0 241 october 01, 2007 preliminary lm3s600 microcontroller
register 13: uart peripheral identification 4 (uartperiphid4), offset 0xfd0 the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. uar t peripheral identification 4 (uar tperiphid4) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0xfd0 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid4 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 uar t peripheral id register[7:0] can be used by software to identify the presence of this peripheral. 0x0000 ro pid4 7:0 october 01, 2007 242 preliminary universal asynchronous receivers/t ransmitters (uar t s)
register 14: uart peripheral identification 5 (uartperiphid5), offset 0xfd4 the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. uar t peripheral identification 5 (uar tperiphid5) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0xfd4 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid5 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 uar t peripheral id register[15:8] can be used by software to identify the presence of this peripheral. 0x0000 ro pid5 7:0 243 october 01, 2007 preliminary lm3s600 microcontroller
register 15: uart peripheral identification 6 (uartperiphid6), offset 0xfd8 the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. uar t peripheral identification 6 (uar tperiphid6) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0xfd8 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid6 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 uar t peripheral id register[23:16] can be used by software to identify the presence of this peripheral. 0x0000 ro pid6 7:0 october 01, 2007 244 preliminary universal asynchronous receivers/t ransmitters (uar t s)
register 16: uart peripheral identification 7 (uartperiphid7), offset 0xfdc the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. uar t peripheral identification 7 (uar tperiphid7) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0xfdc t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid7 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:8 uar t peripheral id register[31:24] can be used by software to identify the presence of this peripheral. 0x0000 ro pid7 7:0 245 october 01, 2007 preliminary lm3s600 microcontroller
register 17: uart peripheral identification 0 (uartperiphid0), offset 0xfe0 the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. uar t peripheral identification 0 (uar tperiphid0) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0xfe0 t ype ro, reset 0x0000.001 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 uar t peripheral id register[7:0] can be used by software to identify the presence of this peripheral. 0x1 1 ro pid0 7:0 october 01, 2007 246 preliminary universal asynchronous receivers/t ransmitters (uar t s)
register 18: uart peripheral identification 1 (uartperiphid1), offset 0xfe4 the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. uar t peripheral identification 1 (uar tperiphid1) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0xfe4 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 uar t peripheral id register[15:8] can be used by software to identify the presence of this peripheral. 0x00 ro pid1 7:0 247 october 01, 2007 preliminary lm3s600 microcontroller
register 19: uart peripheral identification 2 (uartperiphid2), offset 0xfe8 the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. uar t peripheral identification 2 (uar tperiphid2) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0xfe8 t ype ro, reset 0x0000.0018 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 uar t peripheral id register[23:16] can be used by software to identify the presence of this peripheral. 0x18 ro pid2 7:0 october 01, 2007 248 preliminary universal asynchronous receivers/t ransmitters (uar t s)
register 20: uart peripheral identification 3 (uartperiphid3), offset 0xfec the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. uar t peripheral identification 3 (uar tperiphid3) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0xfec t ype ro, reset 0x0000.0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 uar t peripheral id register[31:24] can be used by software to identify the presence of this peripheral. 0x01 ro pid3 7:0 249 october 01, 2007 preliminary lm3s600 microcontroller
register 21: uart primecell identification 0 (uartpcellid0), offset 0xff0 the uartpcellidn registers are hard-coded and the fields within the registers determine the reset values. uar t primecell identification 0 (uar tpcellid0) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0xff0 t ype ro, reset 0x0000.000d 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 uar t primecell id register[7:0] provides software a standard cross-peripheral identification system. 0x0d ro cid0 7:0 october 01, 2007 250 preliminary universal asynchronous receivers/t ransmitters (uar t s)
register 22: uart primecell identification 1 (uartpcellid1), offset 0xff4 the uartpcellidn registers are hard-coded and the fields within the registers determine the reset values. uar t primecell identification 1 (uar tpcellid1) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0xff4 t ype ro, reset 0x0000.00f0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 uar t primecell id register[15:8] provides software a standard cross-peripheral identification system. 0xf0 ro cid1 7:0 251 october 01, 2007 preliminary lm3s600 microcontroller
register 23: uart primecell identification 2 (uartpcellid2), offset 0xff8 the uartpcellidn registers are hard-coded and the fields within the registers determine the reset values. uar t primecell identification 2 (uar tpcellid2) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0xff8 t ype ro, reset 0x0000.0005 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 uar t primecell id register[23:16] provides software a standard cross-peripheral identification system. 0x05 ro cid2 7:0 october 01, 2007 252 preliminary universal asynchronous receivers/t ransmitters (uar t s)
register 24: uart primecell identification 3 (uartpcellid3), offset 0xffc the uartpcellidn registers are hard-coded and the fields within the registers determine the reset values. uar t primecell identification 3 (uar tpcellid3) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0xffc t ype ro, reset 0x0000.00b1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 uar t primecell id register[31:24] provides software a standard cross-peripheral identification system. 0xb1 ro cid3 7:0 253 october 01, 2007 preliminary lm3s600 microcontroller
12 synchronous serial interface (ssi) the stellaris ? synchronous serial interface (ssi) is a master or slave interface for synchronous serial communication with peripheral devices that have either freescale spi, microwire, or t exas instruments synchronous serial interfaces. the stellaris ? ssi module has the following features: master or slave operation programmable clock bit rate and prescale separate transmit and receive fifos, 16 bits wide, 8 locations deep programmable interface operation for freescale spi, microwire, or t exas instruments synchronous serial interfaces programmable data frame size from 4 to 16 bits internal loopback test mode for diagnostic/debug testing 12.1 block diagram figure 12-1. ssi module block diagram 12.2 functional description the ssi performs serial-to-parallel conversion on data received from a peripheral device. the cpu accesses data, control, and status information. the transmit and receive paths are buf fered with october 01, 2007 254 preliminary synchronous serial interface (ssi) t ransmit / receive logic clock prescaler ssicpsr control / status ssicr 0 ssicr 1 ssisr interrupt control ssiim ssimis ssiris ssiicr ssidr txfifo 8 x 16 . . . rxfifo 8 x 16 . . . system clock ssitx ssirx ssiclk ssifss interrupt identification registers ssipcellid 0 ssiperiphid 0 ssiperiphid 4 ssipcellid 1 ssiperiphid 1 ssiperiphid 5 ssipcellid 2 ssiperiphid 2 ssiperiphid 6 ssipcellid 3 ssiperiphid 3 ssiperiphid 7
internal fifo memories allowing up to eight 16-bit values to be stored independently in both transmit and receive modes. 12.2.1 bit rate generation the ssi includes a programmable bit rate clock divider and prescaler to generate the serial output clock. bit rates are supported to 2 mhz and higher , although maximum bit rate is determined by peripheral devices. the serial bit rate is derived by dividing down the 50-mhz input clock. the clock is first divided by an even prescale value cpsdvsr from 2 to 254, which is programmed in the ssi clock prescale (ssicpsr) register (see page 273 ). the clock is further divided by a value from 1 to 256, which is 1 + scr , where scr is the value programmed in the ssi control0 (ssicr0) register (see page 266 ). the frequency of the output clock ssiclk is defined by: fssiclk = fsysclk / (cpsdvsr * (1 + scr)) note that although the ssiclk transmit clock can theoretically be 25 mhz, the module may not be able to operate at that speed. for master mode, the system clock must be at least two times faster than the ssiclk . for slave mode, the system clock must be at least 12 times faster than the ssiclk . see synchronous serial interface (ssi) on page 352 to view ssi timing parameters. 12.2.2 fifo operation 12.2.2.1 t ransmit fifo the common transmit fifo is a 16-bit wide, 8-locations deep, first-in, first-out memory buf fer . the cpu writes data to the fifo by writing the ssi data (ssidr) register (see page 270 ), and data is stored in the fifo until it is read out by the transmission logic. when configured as a master or a slave, parallel data is written into the transmit fifo prior to serial conversion and transmission to the attached slave or master , respectively , through the ssitx pin. 12.2.2.2 receive fifo the common receive fifo is a 16-bit wide, 8-locations deep, first-in, first-out memory buf fer . received data from the serial interface is stored in the buf fer until read out by the cpu, which accesses the read fifo by reading the ssidr register . when configured as a master or slave, serial data received through the ssirx pin is registered prior to parallel loading into the attached slave or master receive fifo, respectively . 12.2.3 interrupts the ssi can generate interrupts when the following conditions are observed: t ransmit fifo service receive fifo service receive fifo time-out receive fifo overrun all of the interrupt events are ored together before being sent to the interrupt controller , so the ssi can only generate a single interrupt request to the controller at any given time. y ou can mask each 255 october 01, 2007 preliminary lm3s600 microcontroller
of the four individual maskable interrupts by setting the appropriate bits in the ssi interrupt mask (ssiim) register (see page 274 ). setting the appropriate mask bit to 1 enables the interrupt. provision of the individual outputs, as well as a combined interrupt output, allows use of either a global interrupt service routine, or modular device drivers to handle interrupts. the transmit and receive dynamic dataflow interrupts have been separated from the status interrupts so that data can be read or written in response to the fifo trigger levels. the status of the individual interrupt sources can be read from the ssi raw interrupt status (ssiris) and ssi masked interrupt status (ssimis) registers (see page 276 and page 277 , respectively). 12.2.4 frame formats each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is transmitted starting with the msb. there are three basic frame types that can be selected: t exas instruments synchronous serial freescale spi microwire for all three formats, the serial clock ( ssiclk ) is held inactive while the ssi is idle, and ssiclk transitions at the programmed frequency only during active transmission or reception of data. the idle state of ssiclk is utilized to provide a receive timeout indication that occurs when the receive fifo still contains data after a timeout period. for freescale spi and microwire frame formats, the serial frame ( ssifss ) pin is active low , and is asserted (pulled down) during the entire transmission of the frame. for t exas instruments synchronous serial frame format, the ssifss pin is pulsed for one serial clock period starting at its rising edge, prior to the transmission of each frame. for this frame format, both the ssi and the of f-chip slave device drive their output data on the rising edge of ssiclk , and latch data from the other device on the falling edge. unlike the full-duplex transmission of the other two frame formats, the microwire format uses a special master-slave messaging technique, which operates at half-duplex. in this mode, when a frame begins, an 8-bit control message is transmitted to the of f-chip slave. during this transmit, no incoming data is received by the ssi. after the message has been sent, the of f-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the requested data. the returned data can be 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. 12.2.4.1 t exas instruments synchronous serial frame format figure 12-2 on page 256 shows the t exas instruments synchronous serial frame format for a single transmitted frame. figure 12-2. ti synchronous serial frame format (single t ransfer) october 01, 2007 256 preliminary synchronous serial interface (ssi) s s i c l k 4 t o 1 6 b i t s s s i f s s s s i t x / s s i r x m s b l s b
in this mode, ssiclk and ssifss are forced low , and the transmit data line ssitx is tristated whenever the ssi is idle. once the bottom entry of the transmit fifo contains data, ssifss is pulsed high for one ssiclk period. the value to be transmitted is also transferred from the transmit fifo to the serial shift register of the transmit logic. on the next rising edge of ssiclk , the msb of the 4 to 16-bit data frame is shifted out on the ssitx pin. likewise, the msb of the received data is shifted onto the ssirx pin by the of f-chip serial slave device. both the ssi and the of f-chip serial slave device then clock each data bit into their serial shifter on the falling edge of each ssiclk . the received data is transferred from the serial shifter to the receive fifo on the first rising edge of ssiclk after the lsb has been latched. figure 12-3 on page 257 shows the t exas instruments synchronous serial frame format when back-to-back frames are transmitted. figure 12-3. ti synchronous serial frame format (continuous t ransfer) 12.2.4.2 freescale spi frame format the freescale spi interface is a four-wire interface where the ssifss signal behaves as a slave select. the main feature of the freescale spi format is that the inactive state and phase of the ssiclk signal are programmable through the spo and sph bits within the ssiscr0 control register . spo clock polarity bit when the spo clock polarity control bit is low , it produces a steady state low value on the ssiclk pin. if the spo bit is high, a steady state high value is placed on the ssiclk pin when data is not being transferred. sph phase control bit the sph phase control bit selects the clock edge that captures data and allows it to change state. it has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. when the sph phase control bit is low , data is captured on the first clock edge transition. if the sph bit is high, data is captured on the second clock edge transition. 12.2.4.3 freescale spi frame format with spo=0 and sph=0 single and continuous transmission signal sequences for freescale spi format with spo=0 and sph=0 are shown in figure 12-4 on page 258 and figure 12-5 on page 258 . 257 october 01, 2007 preliminary lm3s600 microcontroller m s b l s b 4 t o 1 6 b i t s s s i c l k s s i f s s s s i t x / s s i r x
figure 12-4. freescale spi format (single t ransfer) with spo=0 and sph=0 note: q is undefined. figure 12-5. freescale spi format (continuous t ransfer) with spo=0 and sph=0 in this configuration, during idle periods: ssiclk is forced low ssifss is forced high the transmit data line ssitx is arbitrarily forced low when the ssi is configured as a master , it enables the ssiclk pad when the ssi is configured as a slave, it disables the ssiclk pad if the ssi is enabled and there is valid data within the transmit fifo, the start of transmission is signified by the ssifss master signal being driven low . this causes slave data to be enabled onto the ssirx input line of the master . the master ssitx output pad is enabled. one half ssiclk period later , valid master data is transferred to the ssitx pin. now that both the master and slave data have been set, the ssiclk master clock pin goes high after one further half ssiclk period. the data is now captured on the rising and propagated on the falling edges of the ssiclk signal. in the case of a single word transmission, after all bits of the data word have been transferred, the ssifss line is returned to its idle high state one ssiclk period after the last bit has been captured. however , in the case of continuous back-to-back transmissions, the ssifss signal must be pulsed high between each data word transfer . this is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the sph bit is logic zero. therefore, the master device must raise the ssifss pin of the slave device between each data transfer to enable the serial peripheral data write. on completion of the continuous transfer , the ssifss pin is returned to its idle state one ssiclk period after the last bit has been captured. october 01, 2007 258 preliminary synchronous serial interface (ssi) 4 t o 1 6 b i t s s s i c l k s s i f s s s s i r x q s s i t x m s b m s b l s b l s b s s i c l k s s i f s s s s i r x l s b s s i t x m s b l s b 4 t o 1 6 b i t s l s b m s b m s b m s b l s b
12.2.4.4 freescale spi frame format with spo=0 and sph=1 the transfer signal sequence for freescale spi format with spo=0 and sph=1 is shown in figure 12-6 on page 259 , which covers both single and continuous transfers. figure 12-6. freescale spi frame format with spo=0 and sph=1 note: q is undefined. in this configuration, during idle periods: ssiclk is forced low ssifss is forced high the transmit data line ssitx is arbitrarily forced low when the ssi is configured as a master , it enables the ssiclk pad when the ssi is configured as a slave, it disables the ssiclk pad if the ssi is enabled and there is valid data within the transmit fifo, the start of transmission is signified by the ssifss master signal being driven low . the master ssitx output is enabled. after a further one half ssiclk period, both master and slave valid data is enabled onto their respective transmission lines. at the same time, the ssiclk is enabled with a rising edge transition. data is then captured on the falling edges and propagated on the rising edges of the ssiclk signal. in the case of a single word transfer , after all bits have been transferred, the ssifss line is returned to its idle high state one ssiclk period after the last bit has been captured. for continuous back-to-back transfers, the ssifss pin is held low between successive data words and termination is the same as that of the single word transfer . 12.2.4.5 freescale spi frame format with spo=1 and sph=0 single and continuous transmission signal sequences for freescale spi format with spo=1 and sph=0 are shown in figure 12-7 on page 260 and figure 12-8 on page 260 . 259 october 01, 2007 preliminary lm3s600 microcontroller 4 t o 1 6 b i t s s s i c l k s s i f s s s s i r x s s i t x q m s b q m s b l s b l s b
figure 12-7. freescale spi frame format (single t ransfer) with spo=1 and sph=0 note: q is undefined. figure 12-8. freescale spi frame format (continuous t ransfer) with spo=1 and sph=0 in this configuration, during idle periods: ssiclk is forced high ssifss is forced high the transmit data line ssitx is arbitrarily forced low when the ssi is configured as a master , it enables the ssiclk pad when the ssi is configured as a slave, it disables the ssiclk pad if the ssi is enabled and there is valid data within the transmit fifo, the start of transmission is signified by the ssifss master signal being driven low , which causes slave data to be immediately transferred onto the ssirx line of the master . the master ssitx output pad is enabled. one half period later , valid master data is transferred to the ssitx line. now that both the master and slave data have been set, the ssiclk master clock pin becomes low after one further half ssiclk period. this means that data is captured on the falling edges and propagated on the rising edges of the ssiclk signal. in the case of a single word transmission, after all bits of the data word are transferred, the ssifss line is returned to its idle high state one ssiclk period after the last bit has been captured. however , in the case of continuous back-to-back transmissions, the ssifss signal must be pulsed high between each data word transfer . this is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the sph bit is logic zero. therefore, the master device must raise the ssifss pin of the slave device between each data transfer to enable the serial peripheral data write. on completion of the continuous transfer , the ssifss pin is returned to its idle state one ssiclk period after the last bit has been captured. october 01, 2007 260 preliminary synchronous serial interface (ssi) 4 t o 1 6 b i t s s s i c l k s s i f s s s s i r x s s i t x q m s b m s b l s b l s b s s i c l k s s i f s s s s i t x / s s i r x m s b l s b 4 t o 1 6 b i t s l s b m s b
12.2.4.6 freescale spi frame format with spo=1 and sph=1 the transfer signal sequence for freescale spi format with spo=1 and sph=1 is shown in figure 12-9 on page 261 , which covers both single and continuous transfers. figure 12-9. freescale spi frame format with spo=1 and sph=1 note: q is undefined. in this configuration, during idle periods: ssiclk is forced high ssifss is forced high the transmit data line ssitx is arbitrarily forced low when the ssi is configured as a master , it enables the ssiclk pad when the ssi is configured as a slave, it disables the ssiclk pad if the ssi is enabled and there is valid data within the transmit fifo, the start of transmission is signified by the ssifss master signal being driven low . the master ssitx output pad is enabled. after a further one-half ssiclk period, both master and slave data are enabled onto their respective transmission lines. at the same time, ssiclk is enabled with a falling edge transition. data is then captured on the rising edges and propagated on the falling edges of the ssiclk signal. after all bits have been transferred, in the case of a single word transmission, the ssifss line is returned to its idle high state one ssiclk period after the last bit has been captured. for continuous back-to-back transmissions, the ssifss pin remains in its active low state, until the final bit of the last word has been captured, and then returns to its idle state as described above. for continuous back-to-back transfers, the ssifss pin is held low between successive data words and termination is the same as that of the single word transfer . 12.2.4.7 microwire frame format figure 12-10 on page 262 shows the microwire frame format, again for a single frame. figure 12-1 1 on page 263 shows the same format when back-to-back frames are transmitted. 261 october 01, 2007 preliminary lm3s600 microcontroller 4 t o 1 6 b i t s s s i c l k s s i f s s s s i r x s s i t x q q m s b m s b l s b l s b
figure 12-10. microwire frame format (single frame) microwire format is very similar to spi format, except that transmission is half-duplex instead of full-duplex, using a master-slave message passing technique. each serial transmission begins with an 8-bit control word that is transmitted from the ssi to the of f-chip slave device. during this transmission, no incoming data is received by the ssi. after the message has been sent, the of f-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the required data. the returned data is 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. in this configuration, during idle periods: ssiclk is forced low ssifss is forced high the transmit data line ssitx is arbitrarily forced low a transmission is triggered by writing a control byte to the transmit fifo. the falling edge of ssifss causes the value contained in the bottom entry of the transmit fifo to be transferred to the serial shift register of the transmit logic, and the msb of the 8-bit control frame to be shifted out onto the ssitx pin. ssifss remains low for the duration of the frame transmission. the ssirx pin remains tristated during this transmission. the of f-chip serial slave device latches each control bit into its serial shifter on the rising edge of each ssiclk . after the last bit is latched by the slave device, the control byte is decoded during a one clock wait-state, and the slave responds by transmitting data back to the ssi. each bit is driven onto the ssirx line on the falling edge of ssiclk . the ssi in turn latches each bit on the rising edge of ssiclk . at the end of the frame, for single transfers, the ssifss signal is pulled high one clock period after the last bit has been latched in the receive serial shifter , which causes the data to be transferred to the receive fifo. note: the of f-chip slave device can tristate the receive line either on the falling edge of ssiclk after the lsb has been latched by the receive shifter , or when the ssifss pin goes high. for continuous transfers, data transmission begins and ends in the same manner as a single transfer . however , the ssifss line is continuously asserted (held low) and transmission of data occurs back-to-back. the control byte of the next frame follows directly after the lsb of the received data from the current frame. each of the received values is transferred from the receive shifter on the falling edge of ssiclk , after the lsb of the frame has been latched into the ssi. october 01, 2007 262 preliminary synchronous serial interface (ssi) s s i c l k s s i f s s l s b m s b s s i r x 4 t o 1 6 b i t s o u t p u t d a t a 0 s s i t x m s b l s b 8 - b i t c o n t r o l
figure 12-1 1. microwire frame format (continuous t ransfer) in the microwire mode, the ssi slave samples the first bit of receive data on the rising edge of ssiclk after ssifss has gone low . masters that drive a free-running ssiclk must ensure that the ssifss signal has suf ficient setup and hold margins with respect to the rising edge of ssiclk . figure 12-12 on page 263 illustrates these setup and hold time requirements. with respect to the ssiclk rising edge on which the first bit of receive data is to be sampled by the ssi slave, ssifss must have a setup of at least two times the period of ssiclk on which the ssi operates. with respect to the ssiclk rising edge previous to this edge, ssifss must have a hold of at least one ssiclk period. figure 12-12. microwire frame format, ssifss input setup and hold requirements 12.3 initialization and configuration t o use the ssi, its peripheral clock must be enabled by setting the ssi bit in the rcgc1 register . for each of the frame formats, the ssi is configured using the following steps: 1. ensure that the sse bit in the ssicr1 register is disabled before making any configuration changes. 2. select whether the ssi is a master or slave: a. for master operations, set the ssicr1 register to 0x0000.0000. b. for slave mode (output enabled), set the ssicr1 register to 0x0000.0004. c. for slave mode (output disabled), set the ssicr1 register to 0x0000.000c. 3. configure the clock prescale divisor by writing the ssicpsr register . 263 october 01, 2007 preliminary lm3s600 microcontroller 8 - b i t c o n t r o l s s i c l k s s i f s s l s b m s b s s i r x 4 t o 1 6 b i t s o u t p u t d a t a 0 s s i t x m s b l s b l s b m s b s s i c l k s s i f s s s s i r x f i r s t r x d a t a t o b e s a m p l e d b y s s i s l a v e t s e t u p = ( 2 * t s s i c l k ) t h o l d = t s s i c l k
4. w rite the ssicr0 register with the following configuration: serial clock rate ( scr ) desired clock phase/polarity , if using freescale spi mode ( sph and spo ) the protocol mode: freescale spi, ti ssf , microwire ( frf ) the data size ( dss ) 5. enable the ssi by setting the sse bit in the ssicr1 register . as an example, assume the ssi must be configured to operate with the following parameters: master operation freescale spi mode (spo=1, sph=1) 1 mbps bit rate 8 data bits assuming the system clock is 20 mhz, the bit rate calculation would be: fssiclk = fsysclk / (cpsdvsr * (1 + scr)) 1x106 = 20x106 / (cpsdvsr * (1 + scr)) in this case, if cpsdvsr =2, scr must be 9. the configuration sequence would be as follows: 1. ensure that the sse bit in the ssicr1 register is disabled. 2. w rite the ssicr1 register with a value of 0x0000.0000. 3. w rite the ssicpsr register with a value of 0x0000.0002. 4. w rite the ssicr0 register with a value of 0x0000.09c7. 5. the ssi is then enabled by setting the sse bit in the ssicr1 register to 1. 12.4 register map t able 12-1 on page 264 lists the ssi registers. the of fset listed is a hexadecimal increment to the register s address, relative to that ssi module s base address: ssi0: 0x4000.8000 note: the ssi must be disabled (see the sse bit in the ssicr1 register) before any of the control registers are reprogrammed. t able 12-1. ssi register map see page description reset t ype name offset 266 ssi control 0 0x0000.0000 r/w ssicr0 0x000 october 01, 2007 264 preliminary synchronous serial interface (ssi)
see page description reset t ype name offset 268 ssi control 1 0x0000.0000 r/w ssicr1 0x004 270 ssi data 0x0000.0000 r/w ssidr 0x008 271 ssi status 0x0000.0003 ro ssisr 0x00c 273 ssi clock prescale 0x0000.0000 r/w ssicpsr 0x010 274 ssi interrupt mask 0x0000.0000 r/w ssiim 0x014 276 ssi raw interrupt status 0x0000.0008 ro ssiris 0x018 277 ssi masked interrupt status 0x0000.0000 ro ssimis 0x01c 278 ssi interrupt clear 0x0000.0000 w1c ssiicr 0x020 279 ssi peripheral identification 4 0x0000.0000 ro ssiperiphid4 0xfd0 280 ssi peripheral identification 5 0x0000.0000 ro ssiperiphid5 0xfd4 281 ssi peripheral identification 6 0x0000.0000 ro ssiperiphid6 0xfd8 282 ssi peripheral identification 7 0x0000.0000 ro ssiperiphid7 0xfdc 283 ssi peripheral identification 0 0x0000.0022 ro ssiperiphid0 0xfe0 284 ssi peripheral identification 1 0x0000.0000 ro ssiperiphid1 0xfe4 285 ssi peripheral identification 2 0x0000.0018 ro ssiperiphid2 0xfe8 286 ssi peripheral identification 3 0x0000.0001 ro ssiperiphid3 0xfec 287 ssi primecell identification 0 0x0000.000d ro ssipcellid0 0xff0 288 ssi primecell identification 1 0x0000.00f0 ro ssipcellid1 0xff4 289 ssi primecell identification 2 0x0000.0005 ro ssipcellid2 0xff8 290 ssi primecell identification 3 0x0000.00b1 ro ssipcellid3 0xffc 12.5 register descriptions the remainder of this section lists and describes the ssi registers, in numerical order by address of fset. 265 october 01, 2007 preliminary lm3s600 microcontroller
register 1: ssi control 0 (ssicr0), offset 0x000 ssicr0 is control register 0 and contains bit fields that control various functions within the ssi module. functionality such as protocol mode, clock rate, and data size are configured in this register . ssi control 0 (ssicr0) ssi0 base: 0x4000.8000 of fset 0x000 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 dss frf spo sph scr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:16 ssi serial clock rate the value scr is used to generate the transmit and receive bit rate of the ssi. the bit rate is: br=fssiclk/(cpsdvsr * (1 + scr)) where cpsdvsr is an even value from 2-254 programmed in the ssicpsr register , and scr is a value from 0-255. 0x0000 r/w scr 15:8 ssi serial clock phase this bit is only applicable to the freescale spi format. the sph control bit selects the clock edge that captures data and allows it to change state. it has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. when the sph bit is 0, data is captured on the first clock edge transition. if sph is 1, data is captured on the second clock edge transition. 0 r/w sph 7 ssi serial clock polarity this bit is only applicable to the freescale spi format. when the spo bit is 0, it produces a steady state low value on the ssiclk pin. if spo is 1, a steady state high value is placed on the ssiclk pin when data is not being transferred. 0 r/w spo 6 october 01, 2007 266 preliminary synchronous serial interface (ssi)
description reset t ype name bit/field ssi frame format select the frf values are defined as follows: frame format v alue freescale spi frame format 0x0 t exas intruments synchronous serial frame format 0x1 microwire frame format 0x2 reserved 0x3 0x0 r/w frf 5:4 ssi data size select the dss values are defined as follows: data size v alue reserved 0x0-0x2 4-bit data 0x3 5-bit data 0x4 6-bit data 0x5 7-bit data 0x6 8-bit data 0x7 9-bit data 0x8 10-bit data 0x9 1 1-bit data 0xa 12-bit data 0xb 13-bit data 0xc 14-bit data 0xd 15-bit data 0xe 16-bit data 0xf 0x00 r/w dss 3:0 267 october 01, 2007 preliminary lm3s600 microcontroller
register 2: ssi control 1 (ssicr1), offset 0x004 ssicr1 is control register 1 and contains bit fields that control various functions within the ssi module. master and slave mode functionality is controlled by this register . ssi control 1 (ssicr1) ssi0 base: 0x4000.8000 of fset 0x004 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 lbm sse ms sod reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:4 ssi slave mode output disable this bit is relevant only in the slave mode ( ms =1). in multiple-slave systems, it is possible for the ssi master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto the serial output line. in such systems, the txd lines from multiple slaves could be tied together . t o operate in such a system, the sod bit can be configured so that the ssi slave does not drive the ssitx pin. the sod values are defined as follows: description v alue ssi can drive ssitx output in slave output mode. 0 ssi must not drive the ssitx output in slave mode. 1 0 r/w sod 3 ssi master/slave select this bit selects master or slave mode and can be modified only when ssi is disabled ( sse =0). the ms values are defined as follows: description v alue device configured as a master . 0 device configured as a slave. 1 0 r/w ms 2 october 01, 2007 268 preliminary synchronous serial interface (ssi)
description reset t ype name bit/field ssi synchronous serial port enable setting this bit enables ssi operation. the sse values are defined as follows: description v alue ssi operation disabled. 0 ssi operation enabled. 1 note: this bit must be set to 0 before any control registers are reprogrammed. 0 r/w sse 1 ssi loopback mode setting this bit enables loopback t est mode. the lbm values are defined as follows: description v alue normal serial port operation enabled. 0 output of the transmit serial shift register is connected internally to the input of the receive serial shift register . 1 0 r/w lbm 0 269 october 01, 2007 preliminary lm3s600 microcontroller
register 3: ssi data (ssidr), offset 0x008 ssidr is the data register and is 16-bits wide. when ssidr is read, the entry in the receive fifo (pointed to by the current fifo read pointer) is accessed. as data values are removed by the ssi receive logic from the incoming data frame, they are placed into the entry in the receive fifo (pointed to by the current fifo write pointer). when ssidr is written to, the entry in the transmit fifo (pointed to by the write pointer) is written to. data values are removed from the transmit fifo one value at a time by the transmit logic. it is loaded into the transmit serial shifter , then serially shifted out onto the ssitx pin at the programmed bit rate. when a data size of less than 16 bits is selected, the user must right-justify data written to the transmit fifo. the transmit logic ignores the unused bits. received data less than 16 bits is automatically right-justified in the receive buf fer . when the ssi is programmed for microwire frame format, the default size for transmit data is eight bits (the most significant byte is ignored). the receive data size is controlled by the programmer . the transmit fifo and the receive fifo are not cleared even when the sse bit in the ssicr1 register is set to zero. this allows the software to fill the transmit fifo before enabling the ssi. ssi data (ssidr) ssi0 base: 0x4000.8000 of fset 0x008 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 da t a r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 ssi receive/t ransmit data a read operation reads the receive fifo. a write operation writes the transmit fifo. software must right-justify data when the ssi is programmed for a data size that is less than 16 bits. unused bits at the top are ignored by the transmit logic. the receive logic automatically right-justifies the data. 0x0000 r/w da t a 15:0 october 01, 2007 270 preliminary synchronous serial interface (ssi)
register 4: ssi status (ssisr), offset 0x00c ssisr is a status register that contains bits that indicate the fifo fill status and the ssi busy status. ssi status (ssisr) ssi0 base: 0x4000.8000 of fset 0x00c t ype ro, reset 0x0000.0003 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 tfe tnf rne rff bsy reserved r0 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:5 ssi busy bit the bsy values are defined as follows: description v alue ssi is idle. 0 ssi is currently transmitting and/or receiving a frame, or the transmit fifo is not empty . 1 0 ro bsy 4 ssi receive fifo full the rff values are defined as follows: description v alue receive fifo is not full. 0 receive fifo is full. 1 0 ro rff 3 ssi receive fifo not empty the rne values are defined as follows: description v alue receive fifo is empty . 0 receive fifo is not empty . 1 0 ro rne 2 ssi t ransmit fifo not full the tnf values are defined as follows: description v alue t ransmit fifo is full. 0 t ransmit fifo is not full. 1 1 ro tnf 1 271 october 01, 2007 preliminary lm3s600 microcontroller
description reset t ype name bit/field ssi t ransmit fifo empty the tfe values are defined as follows: description v alue t ransmit fifo is not empty . 0 t ransmit fifo is empty . 1 1 r0 tfe 0 october 01, 2007 272 preliminary synchronous serial interface (ssi)
register 5: ssi clock prescale (ssicpsr), offset 0x010 ssicpsr is the clock prescale register and specifies the division factor by which the system clock must be internally divided before further use. the value programmed into this register must be an even number between 2 and 254. the least-significant bit of the programmed number is hard-coded to zero. if an odd number is written to this register , data read back from this register has the least-significant bit as zero. ssi clock prescale (ssicpsr) ssi0 base: 0x4000.8000 of fset 0x010 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cpsdvsr reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 ssi clock prescale divisor this value must be an even number from 2 to 254, depending on the frequency of ssiclk . the lsb always returns 0 on reads. 0x00 r/w cpsdvsr 7:0 273 october 01, 2007 preliminary lm3s600 microcontroller
register 6: ssi interrupt mask (ssiim), offset 0x014 the ssiim register is the interrupt mask set or clear register . it is a read/write register and all bits are cleared to 0 on reset. on a read, this register gives the current value of the mask on the relevant interrupt. a write of 1 to the particular bit sets the mask, enabling the interrupt to be read. a write of 0 clears the corresponding mask. ssi interrupt mask (ssiim) ssi0 base: 0x4000.8000 of fset 0x014 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 rorim r tim rxim txim reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:4 ssi t ransmit fifo interrupt mask the txim values are defined as follows: description v alue tx fifo half-full or less condition interrupt is masked. 0 tx fifo half-full or less condition interrupt is not masked. 1 0 r/w txim 3 ssi receive fifo interrupt mask the tfe values are defined as follows: description v alue rx fifo half-full or more condition interrupt is masked. 0 rx fifo half-full or more condition interrupt is not masked. 1 0 r/w rxim 2 ssi receive t ime-out interrupt mask the rtim values are defined as follows: description v alue rx fifo time-out interrupt is masked. 0 rx fifo time-out interrupt is not masked. 1 0 r/w r tim 1 october 01, 2007 274 preliminary synchronous serial interface (ssi)
description reset t ype name bit/field ssi receive overrun interrupt mask the rorim values are defined as follows: description v alue rx fifo overrun interrupt is masked. 0 rx fifo overrun interrupt is not masked. 1 0 r/w rorim 0 275 october 01, 2007 preliminary lm3s600 microcontroller
register 7: ssi raw interrupt status (ssiris), offset 0x018 the ssiris register is the raw interrupt status register . on a read, this register gives the current raw status value of the corresponding interrupt prior to masking. a write has no ef fect. ssi raw interrupt status (ssiris) ssi0 base: 0x4000.8000 of fset 0x018 t ype ro, reset 0x0000.0008 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 rorris r tris rxris txris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:4 ssi t ransmit fifo raw interrupt status indicates that the transmit fifo is half full or less, when set. 1 ro txris 3 ssi receive fifo raw interrupt status indicates that the receive fifo is half full or more, when set. 0 ro rxris 2 ssi receive t ime-out raw interrupt status indicates that the receive time-out has occurred, when set. 0 ro r tris 1 ssi receive overrun raw interrupt status indicates that the receive fifo has overflowed, when set. 0 ro rorris 0 october 01, 2007 276 preliminary synchronous serial interface (ssi)
register 8: ssi masked interrupt status (ssimis), offset 0x01c the ssimis register is the masked interrupt status register . on a read, this register gives the current masked status value of the corresponding interrupt. a write has no ef fect. ssi masked interrupt status (ssimis) ssi0 base: 0x4000.8000 of fset 0x01c t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 rormis r tmis rxmis txmis reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:4 ssi t ransmit fifo masked interrupt status indicates that the transmit fifo is half full or less, when set. 0 ro txmis 3 ssi receive fifo masked interrupt status indicates that the receive fifo is half full or more, when set. 0 ro rxmis 2 ssi receive t ime-out masked interrupt status indicates that the receive time-out has occurred, when set. 0 ro r tmis 1 ssi receive overrun masked interrupt status indicates that the receive fifo has overflowed, when set. 0 ro rormis 0 277 october 01, 2007 preliminary lm3s600 microcontroller
register 9: ssi interrupt clear (ssiicr), offset 0x020 the ssiicr register is the interrupt clear register . on a write of 1, the corresponding interrupt is cleared. a write of 0 has no ef fect. ssi interrupt clear (ssiicr) ssi0 base: 0x4000.8000 of fset 0x020 t ype w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 roric r tic reserved w1c w1c ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:2 ssi receive t ime-out interrupt clear the rtic values are defined as follows: description v alue no ef fect on interrupt. 0 clears interrupt. 1 0 w1c r tic 1 ssi receive overrun interrupt clear the roric values are defined as follows: description v alue no ef fect on interrupt. 0 clears interrupt. 1 0 w1c roric 0 october 01, 2007 278 preliminary synchronous serial interface (ssi)
register 10: ssi peripheral identification 4 (ssiperiphid4), offset 0xfd0 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. ssi peripheral identification 4 (ssiperiphid4) ssi0 base: 0x4000.8000 of fset 0xfd0 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid4 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 ssi peripheral id register[7:0] can be used by software to identify the presence of this peripheral. 0x00 ro pid4 7:0 279 october 01, 2007 preliminary lm3s600 microcontroller
register 1 1: ssi peripheral identification 5 (ssiperiphid5), offset 0xfd4 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. ssi peripheral identification 5 (ssiperiphid5) ssi0 base: 0x4000.8000 of fset 0xfd4 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid5 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 ssi peripheral id register[15:8] can be used by software to identify the presence of this peripheral. 0x00 ro pid5 7:0 october 01, 2007 280 preliminary synchronous serial interface (ssi)
register 12: ssi peripheral identification 6 (ssiperiphid6), offset 0xfd8 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. ssi peripheral identification 6 (ssiperiphid6) ssi0 base: 0x4000.8000 of fset 0xfd8 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid6 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 ssi peripheral id register[23:16] can be used by software to identify the presence of this peripheral. 0x00 ro pid6 7:0 281 october 01, 2007 preliminary lm3s600 microcontroller
register 13: ssi peripheral identification 7 (ssiperiphid7), offset 0xfdc the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. ssi peripheral identification 7 (ssiperiphid7) ssi0 base: 0x4000.8000 of fset 0xfdc t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid7 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 ssi peripheral id register[31:24] can be used by software to identify the presence of this peripheral. 0x00 ro pid7 7:0 october 01, 2007 282 preliminary synchronous serial interface (ssi)
register 14: ssi peripheral identification 0 (ssiperiphid0), offset 0xfe0 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. ssi peripheral identification 0 (ssiperiphid0) ssi0 base: 0x4000.8000 of fset 0xfe0 t ype ro, reset 0x0000.0022 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:8 ssi peripheral id register[7:0] can be used by software to identify the presence of this peripheral. 0x22 ro pid0 7:0 283 october 01, 2007 preliminary lm3s600 microcontroller
register 15: ssi peripheral identification 1 (ssiperiphid1), offset 0xfe4 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. ssi peripheral identification 1 (ssiperiphid1) ssi0 base: 0x4000.8000 of fset 0xfe4 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 ssi peripheral id register [15:8] can be used by software to identify the presence of this peripheral. 0x00 ro pid1 7:0 october 01, 2007 284 preliminary synchronous serial interface (ssi)
register 16: ssi peripheral identification 2 (ssiperiphid2), offset 0xfe8 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. ssi peripheral identification 2 (ssiperiphid2) ssi0 base: 0x4000.8000 of fset 0xfe8 t ype ro, reset 0x0000.0018 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 ssi peripheral id register [23:16] can be used by software to identify the presence of this peripheral. 0x18 ro pid2 7:0 285 october 01, 2007 preliminary lm3s600 microcontroller
register 17: ssi peripheral identification 3 (ssiperiphid3), offset 0xfec the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. ssi peripheral identification 3 (ssiperiphid3) ssi0 base: 0x4000.8000 of fset 0xfec t ype ro, reset 0x0000.0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 ssi peripheral id register [31:24] can be used by software to identify the presence of this peripheral. 0x01 ro pid3 7:0 october 01, 2007 286 preliminary synchronous serial interface (ssi)
register 18: ssi primecell identification 0 (ssipcellid0), offset 0xff0 the ssipcellidn registers are hard-coded and the fields within the register determine the reset value. ssi primecell identification 0 (ssipcellid0) ssi0 base: 0x4000.8000 of fset 0xff0 t ype ro, reset 0x0000.000d 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 ssi primecell id register [7:0] provides software a standard cross-peripheral identification system. 0x0d ro cid0 7:0 287 october 01, 2007 preliminary lm3s600 microcontroller
register 19: ssi primecell identification 1 (ssipcellid1), offset 0xff4 the ssipcellidn registers are hard-coded and the fields within the register determine the reset value. ssi primecell identification 1 (ssipcellid1) ssi0 base: 0x4000.8000 of fset 0xff4 t ype ro, reset 0x0000.00f0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 ssi primecell id register [15:8] provides software a standard cross-peripheral identification system. 0xf0 ro cid1 7:0 october 01, 2007 288 preliminary synchronous serial interface (ssi)
register 20: ssi primecell identification 2 (ssipcellid2), offset 0xff8 the ssipcellidn registers are hard-coded and the fields within the register determine the reset value. ssi primecell identification 2 (ssipcellid2) ssi0 base: 0x4000.8000 of fset 0xff8 t ype ro, reset 0x0000.0005 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 ssi primecell id register [23:16] provides software a standard cross-peripheral identification system. 0x05 ro cid2 7:0 289 october 01, 2007 preliminary lm3s600 microcontroller
register 21: ssi primecell identification 3 (ssipcellid3), offset 0xffc the ssipcellidn registers are hard-coded and the fields within the register determine the reset value. ssi primecell identification 3 (ssipcellid3) ssi0 base: 0x4000.8000 of fset 0xffc t ype ro, reset 0x0000.00b1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 ssi primecell id register [31:24] provides software a standard cross-peripheral identification system. 0xb1 ro cid3 7:0 october 01, 2007 290 preliminary synchronous serial interface (ssi)
13 inter-integrated circuit (i 2 c) interface the inter-integrated circuit (i 2 c) bus provides bi-directional data transfer through a two-wire design (a serial data line sda and a serial clock line scl), and interfaces to external i 2 c devices such as serial memory (rams and roms), networking devices, lcds, tone generators, and so on. the i 2 c bus may also be used for system testing and diagnostic purposes in product development and manufacture. the lm3s600 microcontroller includes one i 2 c module, providing the ability to interact (both send and receive) with other i 2 c devices on the bus. devices on the i 2 c bus can be designated as either a master or a slave. the stellaris ? i 2 c module supports both sending and receiving data as either a master or a slave, and also supports the simultaneous operation as both a master and a slave. there are a total of four i 2 c modes: master t ransmit, master receive, slave t ransmit, and slave receive. the stellaris ? i 2 c module can operate at two speeds: standard (100 kbps) and fast (400 kbps). both the i 2 c master and slave can generate interrupts; the i 2 c master generates interrupts when a transmit or receive operation completes (or aborts due to an error) and the i 2 c slave generates interrupts when data has been sent or requested by a master . 13.1 block diagram figure 13-1. i 2 c block diagram 13.2 functional description i 2 c module is comprised of both master and slave functions which are implemented as separate peripherals. for proper operation, the sda and scl pins must be connected to bi-directional open-drain pads. a typical i 2 c bus configuration is shown in figure 13-2 on page 292 . see i 2 c on page 351 for i 2 c timing diagrams. 291 october 01, 2007 preliminary lm3s600 microcontroller i 2 c i /o select i 2 c master core interrupt i 2 c slave core i2cscl i2csda i2csda i2cscl i2csda i2cscl i2cmsa i2cmcs i2cmdr i2cmtpr i2cmimr i2cmris i2cmicr i2cmcr i2csoar i2cscsr i2csdr i2csim i2csris i2csmis i2csicr i2cmmis i 2 c control
figure 13-2. i 2 c bus configuration 13.2.1 i 2 c bus functional overview the i 2 c bus uses only two signals: sda and scl, named i2csda and i2cscl on stellaris ? microcontrollers. sda is the bi-directional serial data line and scl is the bi-directional serial clock line. the bus is considered idle when both lines are high. every transaction on the i 2 c bus is nine bits long, consisting of eight data bits and a single acknowledge bit. the number of bytes per transfer (defined as the time between a valid st ar t and st op condition, described in st ar t and st op conditions on page 292 ) is unrestricted, but each byte has to be followed by an acknowledge bit, and data must be transferred msb first. when a receiver cannot receive another complete byte, it can hold the clock line scl low and force the transmitter into a wait state. the data transfer continues when the receiver releases the clock scl. 13.2.1.1 st art and st op conditions the protocol of the i 2 c bus defines two states to begin and end a transaction: st ar t and st op . a high-to-low transition on the sda line while the scl is high is defined as a st ar t condition, and a low-to-high transition on the sda line while scl is high is defined as a st op condition. the bus is considered busy after a st ar t condition and free after a st op condition. see figure 13-3 on page 292 . figure 13-3. st art and st op conditions 13.2.1.2 data format with 7-bit address data transfers follow the format shown in figure 13-4 on page 293 . after the st ar t condition, a slave address is sent. this address is 7-bits long followed by an eighth bit, which is a data direction bit ( r/s bit in the i2cmsa register). a zero indicates a transmit operation (send), and a one indicates a request for data (receive). a data transfer is always terminated by a st op condition generated by the master , however , a master can initiate communications with another device on the bus by generating a repeated st ar t condition and addressing another slave without first generating a st op condition. v arious combinations of receive/send formats are then possible within a single transfer . october 01, 2007 292 preliminary inter-integrated circuit (i 2 c) interface r pup stellar is tm i2cscl i2csd a r pup 3rd p ar ty de vice with i 2 c interf ace scl sd a i 2 c bus scl sd a 3rd p ar ty de vice with i 2 c interf ace scl sd a s t a r t c o n d i t i o n sd a sc l s t o p c o n d i t i o n sd a sc l
figure 13-4. complete data t ransfer with a 7-bit address the first seven bits of the first byte make up the slave address (see figure 13-5 on page 293 ). the eighth bit determines the direction of the message. a zero in the r/s position of the first byte means that the master will write (send) data to the selected slave, and a one in this position means that the master will receive data from the slave. figure 13-5. r/s bit in first byte 13.2.1.3 data v alidity the data on the sda line must be stable during the high period of the clock, and the data line can only change when scl is low (see figure 13-6 on page 293 ). figure 13-6. data v alidity during bit t ransfer on the i 2 c bus 13.2.1.4 acknowledge all bus transactions have a required acknowledge clock cycle that is generated by the master . during the acknowledge cycle, the transmitter (which can be the master or slave) releases the sda line. t o acknowledge the transaction, the receiver must pull down sda during the acknowledge clock cycle. the data sent out by the receiver during the acknowledge cycle must comply with the data validity requirements described in data v alidity on page 293 . when a slave receiver does not acknowledge the slave address, sda must be left high by the slave so that the master can generate a st op condition and abort the current transfer . if the master device is acting as a receiver during a transfer , it is responsible for acknowledging each transfer made by the slave. since the master controls the number of bytes in the transfer , it signals the end of data to the slave transmitter by not generating an acknowledge on the last data byte. the slave transmitter must then release sda to allow the master to generate the st op or a repeated st ar t condition. 293 october 01, 2007 preliminary lm3s600 microcontroller d a t a s l a v e a d d r e s s a c k l s b m s b a c k r / s l s b m s b s d a s c l 1 2 7 8 9 1 2 7 8 9 r / s l s b s l a v e a d d r e s s msb c h a n g e o f d a t a a l l o w e d d a t a l i n e s t a b l e s d a s c l
13.2.1.5 arbitration a master may start a transfer only if the bus is idle. it's possible for two or more masters to generate a st ar t condition within minimum hold time of the st ar t condition. in these situations, an arbitration scheme takes place on the sda line, while scl is high. during arbitration, the first of the competing master devices to place a '1' (high) on sda while another master transmits a '0' (low) will switch of f its data output stage and retire until the bus is idle again. arbitration can take place over several bits. its first stage is a comparison of address bits, and if both masters are trying to address the same device, arbitration continues on to the comparison of data bits. 13.2.2 a vailable speed modes the i 2 c clock rate is determined by the parameters: clk_prd , timer_prd , scl_lp , and scl_hp . where: clk_prd is the system clock period scl_lp is the low phase of scl (fixed at 6) scl_hp is the high phase of scl (fixed at 4) timer_prd is the programmed value in the i 2 c master t imer period (i2cmtpr) register (see page 311 ). the i 2 c clock period is calculated as follows: scl_period = 2*(1 + timer_prd)*(scl_lp + scl_hp)*clk_prd for example: clk_prd = 50 ns timer_prd = 2 scl_lp=6 scl_hp=4 yields a scl frequency of: 1/t = 333 khz t able 13-1 on page 294 gives examples of timer period, system clock, and speed mode (standard or fast). t able 13-1. examples of i 2 c master t imer period versus speed mode fast mode t imer period standard mode t imer period system clock - - 100 kbps 0x01 4 mhz - - 100 kbps 0x02 6 mhz 312 kbps 0x01 89 kbps 0x06 12.5 mhz 278 kbps 0x02 93 kbps 0x08 16.7 mhz 333 kbps 0x02 100 kbps 0x09 20 mhz 312 kbps 0x03 96.2 kbps 0x0c 25 mhz 330 kbps 0x04 97.1 kbps 0x10 33mhz 400 kbps 0x04 100 kbps 0x13 40mhz october 01, 2007 294 preliminary inter-integrated circuit (i 2 c) interface
fast mode t imer period standard mode t imer period system clock 357 kbps 0x06 100 kbps 0x18 50mhz 13.2.3 interrupts the i 2 c can generate interrupts when the following conditions are observed: master transaction completed master transaction error slave transaction received slave transaction requested there is a separate interrupt signal for the i 2 c master and i 2 c modules. while both modules can generate interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt controller . 13.2.3.1 i 2 c master interrupts the i 2 c master module generates an interrupt when a transaction completes (either transmit or receive), or when an error occurs during a transaction. t o enable the i 2 c master interrupt, software must write a '1' to the i 2 c master interrupt mask (i2cmimr) register . when an interrupt condition is met, software must check the error bit in the i 2 c master control/status (i2cmcs) register to verify that an error didn't occur during the last transaction. an error condition is asserted if the last transaction wasn't acknowledge by the slave or if the master was forced to give up ownership of the bus due to a lost arbitration round with another master . if an error is not detected, the application can proceed with the transfer . the interrupt is cleared by writing a '1' to the i 2 c master interrupt clear (i2cmicr) register . if the application doesn't require the use of interrupts, the raw interrupt status is always visible via the i 2 c master raw interrupt status (i2cmris) register . 13.2.3.2 i 2 c slave interrupts the slave module generates interrupts as it receives requests from an i 2 c master . t o enable the i 2 c slave interrupt, write a '1' to the i 2 c slave interrupt mask (i2csimr) register . software determines whether the module should write (transmit) or read (receive) data from the i 2 c slave data (i2csdr) register , by checking the rreq and treq bits of the i 2 c slave control/status (i2cscsr) register . if the slave module is in receive mode and the first byte of a transfer is received, the fbr bit is set along with the rreq bit. the interrupt is cleared by writing a '1' to the i 2 c slave interrupt clear (i2csicr) register . if the application doesn't require the use of interrupts, the raw interrupt status is always visible via the i 2 c slave raw interrupt status (i2csris) register . 13.2.4 loopback operation the i 2 c modules can be placed into an internal loopback mode for diagnostic or debug work. this is accomplished by setting the lpbk bit in the i 2 c master configuration (i2cmcr) register . in loopback mode, the sda and scl signals from the master and slave modules are tied together . 295 october 01, 2007 preliminary lm3s600 microcontroller
13.2.5 command sequence flow charts this section details the steps required to perform the various i 2 c transfer types in both master and slave mode. 13.2.5.1 i 2 c master command sequences the figures that follow show the command sequences available for the i 2 c master . figure 13-7. master single send october 01, 2007 296 preliminary inter-integrated circuit (i 2 c) interface idle w rite slave address to i 2cmsa w rite data to i 2cmdr read i2cmcs sequence may be omitted in a single master system busbsy bit=0? no w rite --- 0 - 111 to i 2cmcs yes read i2cmcs busy bit=0? error bit=0? yes error service idle yes no no
figure 13-8. master single receive 297 october 01, 2007 preliminary lm3s600 microcontroller idle w rite slave address to i 2cmsa read i2cmcs sequence may be omitted in a single master system busbsy bit=0? no w rite --- 00111 to i 2cmcs yes read i2cmcs busy bit=0? error bit=0? yes error service idle no no read data from i 2cmdr yes
figure 13-9. master burst send october 01, 2007 298 preliminary inter-integrated circuit (i 2 c) interface idle w rite slave address to i 2cmsa w rite data to i 2cmdr read i2cmcs busbsy bit=0? yes w rite --- 0 - 011 to i 2cmcs no read i2cmcs busy bit=0? yes error bit=0? yes arblst bit=1? w rite data to i 2cmdr w rite --- 0 - 100 to i 2cmcs index=n? no error service idle yes w rite --- 0 - 001 to i 2cmcs w rite --- 0 - 101 to i 2cmcs yes read i2cmcs busy bit=0? error bit=0? yes no idle yes error service no no no no sequence may be omitted in a single master system
figure 13-10. master burst receive 299 october 01, 2007 preliminary lm3s600 microcontroller idle w rite slave address to i 2cmsa read i2cmcs busbsy bit=0? no w rite --- 01011 to i 2cmcs yes read i2cmcs busy bit=0? no error bit=0? yes arblst bit=1? w rite --- 0 - 100 to i 2cmcs no error service yes idle read data from i 2cmdr index=m-1? w rite --- 00101 to i 2cmcs yes idle read data from i 2cmdr error service error bit=0? yes w rite --- 01001 to i 2cmcs read i2cmcs busy bit=0? no yes sequence may be omitted in a single master system no no no
figure 13-1 1. master burst receive after burst send october 01, 2007 300 preliminary inter-integrated circuit (i 2 c) interface idle master operates in master t ransmit mode st op condition is not generated w rite slave address to i 2cmsa w rite --- 01011 to i 2cmcs master operates in master receive mode idle repeated st ar t condition is generated with changing data direction
figure 13-12. master burst send after burst receive 13.2.5.2 i 2 c slave command sequences figure 13-13 on page 302 presents the command sequence available for the i 2 c slave. 301 october 01, 2007 preliminary lm3s600 microcontroller idle master operates in master receive mode st op condition is not generated w rite slave address to i 2cmsa w rite --- 0 - 011 to i 2cmcs master operates in master t ransmit mode idle repeated st ar t condition is generated with changing data direction
figure 13-13. slave command sequence 13.3 initialization and configuration the following example shows how to configure the i 2 c module to send a single byte as a master . this assumes the system clock is 20 mhz. 1. enable the i 2 c clock by writing a value of 0x0000.1000 to the rcgc1 register in the system control module. 2. enable the clock to the appropriate gpio module via the rcgc2 register in the system control module. 3. in the gpio module, enable the appropriate pins for their alternate function using the gpioafsel register . also, be sure to enable the same pins for open drain operation. 4. initialize the i 2 c master by writing the i2cmcr register with a value of 0x0000.0020. 5. set the desired scl clock speed of 100 kbps by writing the i2cmtpr register with the correct value. the value written to the i2cmtpr register represents the number of system clock periods in one scl clock period. the tpr value is determined by the following equation: october 01, 2007 302 preliminary inter-integrated circuit (i 2 c) interface idle w rite own slave address to i 2csoar w rite ------- 1 to i 2cscsr read i2cscsr rreq bit=1? read data from i 2csdr yes treq bit=1? no w rite data to i 2csdr yes no fbr is also valid
tpr = (system clock / (2 * (scl_lp + scl_hp) * scl_clk)) - 1; tpr = (20mhz / (2 * (6 + 4) * 100000)) - 1; tpr = 9 w rite the i2cmtpr register with the value of 0x0000.0009. 6. specify the slave address of the master and that the next operation will be a send by writing the i2cmsa register with a value of 0x0000.0076. this sets the slave address to 0x3b. 7. place data (byte) to be sent in the data register by writing the i2cmdr register with the desired data. 8. initiate a single byte send of the data from master to slave by writing the i2cmcs register with a value of 0x0000.0007 (st op , st ar t , run). 9. w ait until the transmission completes by polling the i2cmcs register s busbsy bit until it has been cleared. 13.4 i 2 c register map t able 13-2 on page 303 lists the i 2 c registers. all addresses given are relative to the i 2 c base addresses for the master and slave: i 2 c master 0: 0x4002.0000 i 2 c slave 0: 0x4002.0800 t able 13-2. inter-integrated circuit (i 2 c) interface register map see page description reset t ype name offset i 2 c master 305 i2c master slave address 0x0000.0000 r/w i2cmsa 0x000 306 i2c master control/status 0x0000.0000 r/w i2cmcs 0x004 310 i2c master data 0x0000.0000 r/w i2cmdr 0x008 311 i2c master t imer period 0x0000.0001 r/w i2cmtpr 0x00c 312 i2c master interrupt mask 0x0000.0000 r/w i2cmimr 0x010 313 i2c master raw interrupt status 0x0000.0000 ro i2cmris 0x014 314 i2c master masked interrupt status 0x0000.0000 ro i2cmmis 0x018 315 i2c master interrupt clear 0x0000.0000 wo i2cmicr 0x01c 316 i2c master configuration 0x0000.0000 r/w i2cmcr 0x020 i 2 c slave 318 i2c slave own address 0x0000.0000 r/w i2csoar 0x000 319 i2c slave control/status 0x0000.0000 ro i2cscsr 0x004 321 i2c slave data 0x0000.0000 r/w i2csdr 0x008 322 i2c slave interrupt mask 0x0000.0000 r/w i2csimr 0x00c 303 october 01, 2007 preliminary lm3s600 microcontroller
see page description reset t ype name offset 323 i2c slave raw interrupt status 0x0000.0000 ro i2csris 0x010 324 i2c slave masked interrupt status 0x0000.0000 ro i2csmis 0x014 325 i2c slave interrupt clear 0x0000.0000 wo i2csicr 0x018 13.5 register descriptions (i 2 c master) the remainder of this section lists and describes the i 2 c master registers, in numerical order by address of fset. see also register descriptions (i2c slave) on page 317 . october 01, 2007 304 preliminary inter-integrated circuit (i 2 c) interface
register 1: i 2 c master slave address (i2cmsa), offset 0x000 this register consists of eight bits: seven address bits (a6-a0), and a receive/send bit, which determines if the next operation is a receive (high), or send (low). i2c master slave address (i2cmsa) i2c master 0 base: 0x4002.0000 of fset 0x000 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 r/s sa reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 i 2 c slave address this field specifies bits a6 through a0 of the slave address. 0 r/w sa 7:1 receive/send the r/s bit specifies if the next operation is a receive (high) or send (low). 0: send 1: receive 0 r/w r/s 0 305 october 01, 2007 preliminary lm3s600 microcontroller
register 2: i 2 c master control/status (i2cmcs), offset 0x004 this register accesses four control bits when written, and accesses seven status bits when read. the status register consists of seven bits, which when read determine the state of the i 2 c bus controller . the control register consists of four bits: the run , start , stop , and ack bits. the start bit causes the generation of the st ar t , or repea ted st ar t condition. the stop bit determines if the cycle stops at the end of the data cycle, or continues on to a burst. t o generate a single send cycle, the i 2 c master slave address (i2cmsa) register is written with the desired address, the r/s bit is set to 0, and the control register is written with ack =x (0 or 1), stop =1, start =1, and run =1 to perform the operation and stop. when the operation is completed (or aborted due an error), the interrupt pin becomes active and the data may be read from the i2cmdr register . when the i 2 c module operates in master receiver mode, the ack bit must be set normally to logic 1. this causes the i 2 c bus controller to send an acknowledge automatically after each byte. this bit must be reset when the i 2 c bus controller requires no further data to be sent from the slave transmitter . read-only status register i2c master control/status (i2cmcs) i2c master 0 base: 0x4002.0000 of fset 0x004 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 busy error adrack da t ack arblst idle busbsy reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:7 bus busy this bit specifies the state of the i 2 c bus. if set, the bus is busy; otherwise, the bus is idle. the bit changes based on the st ar t and st op conditions. 0 ro busbsy 6 i 2 c idle this bit specifies the i 2 c controller state. if set, the controller is idle; otherwise the controller is not idle. 0 ro idle 5 arbitration lost this bit specifies the result of bus arbitration. if set, the controller lost arbitration; otherwise, the controller won arbitration. 0 ro arblst 4 october 01, 2007 306 preliminary inter-integrated circuit (i 2 c) interface
description reset t ype name bit/field acknowledge data this bit specifies the result of the last data operation. if set, the transmitted data was not acknowledged; otherwise, the data was acknowledged. 0 ro da t ack 3 acknowledge address this bit specifies the result of the last address operation. if set, the transmitted address was not acknowledged; otherwise, the address was acknowledged. 0 ro adrack 2 error this bit specifies the result of the last bus operation. if set, an error occurred on the last operation; otherwise, no error was detected. the error can be from the slave address not being acknowledged, the transmit data not being acknowledged, or because the controller lost arbitration. 0 ro error 1 i 2 c busy this bit specifies the state of the controller . if set, the controller is busy; otherwise, the controller is idle. when the busy bit is set, the other status bits are not valid. 0 ro busy 0 w rite-only control register i2c master control/status (i2cmcs) i2c master 0 base: 0x4002.0000 of fset 0x004 t ype wo, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 run st ar t st op ack reserved wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 wo reserved 31:4 data acknowledge enable when set, causes received data byte to be acknowledged automatically by the master . see field decoding in t able 13-3 on page 308 . 0 wo ack 3 generate st op when set, causes the generation of the st op condition. see field decoding in t able 13-3 on page 308 . 0 wo st op 2 307 october 01, 2007 preliminary lm3s600 microcontroller
description reset t ype name bit/field generate st ar t when set, causes the generation of a st ar t or repeated st ar t condition. see field decoding in t able 13-3 on page 308 . 0 wo st ar t 1 i 2 c master enable when set, allows the master to send or receive data. see field decoding in t able 13-3 on page 308 . 0 wo run 0 t able 13-3. w rite field decoding for i2cmcs[3:0] field (sheet 1 of 3) description i2cmcs[3:0] i2cmsa[0] current state run st art st op ack r/s st ar t condition followed by send (master goes to the master t ransmit state). 1 1 0 x a 0 idle st ar t condition followed by a send and st op condition (master remains in idle state). 1 1 1 x 0 st ar t condition followed by receive operation with negative ack (master goes to the master receive state). 1 1 0 0 1 st ar t condition followed by receive and st op condition (master remains in idle state). 1 1 1 0 1 st ar t condition followed by receive (master goes to the master receive state). 1 1 0 1 1 illegal. 1 1 1 1 1 nop . all other combinations not listed are non-operations. send operation (master remains in master t ransmit state). 1 0 0 x x master t ransmit st op condition (master goes to idle state). 0 0 1 x x send followed by st op condition (master goes to idle state). 1 0 1 x x repeated st ar t condition followed by a send (master remains in master t ransmit state). 1 1 0 x 0 repeated st ar t condition followed by send and st op condition (master goes to idle state). 1 1 1 x 0 repeated st ar t condition followed by a receive operation with a negative ack (master goes to master receive state). 1 1 0 0 1 repeated st ar t condition followed by a send and st op condition (master goes to idle state). 1 1 1 0 1 repeated st ar t condition followed by receive (master goes to master receive state). 1 1 0 1 1 illegal. 1 1 1 1 1 nop . all other combinations not listed are non-operations. october 01, 2007 308 preliminary inter-integrated circuit (i 2 c) interface
description i2cmcs[3:0] i2cmsa[0] current state run st art st op ack r/s receive operation with negative ack (master remains in master receive state). 1 0 0 0 x master receive st op condition (master goes to idle state). b 0 0 1 x x receive followed by st op condition (master goes to idle state). 1 0 1 0 x receive operation (master remains in master receive state). 1 0 0 1 x illegal. 1 0 1 1 x repeated st ar t condition followed by receive operation with a negative ack (master remains in master receive state). 1 1 0 0 1 repeated st ar t condition followed by receive and st op condition (master goes to idle state). 1 1 1 0 1 repeated st ar t condition followed by receive (master remains in master receive state). 1 1 0 1 1 repeated st ar t condition followed by send (master goes to master t ransmit state). 1 1 0 x 0 repeated st ar t condition followed by send and st op condition (master goes to idle state). 1 1 1 x 0 nop . all other combinations not listed are non-operations. a. an x in a table cell indicates the bit can be 0 or 1. b. in master receive mode, a st op condition should be generated only after a data negative acknowledge executed by the master or an address negative acknowledge executed by the slave. 309 october 01, 2007 preliminary lm3s600 microcontroller
register 3: i 2 c master data (i2cmdr), offset 0x008 this register contains the data to be transmitted when in the master t ransmit state, and the data received when in the master receive state. i2c master data (i2cmdr) i2c master 0 base: 0x4002.0000 of fset 0x008 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 da t a reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 data t ransferred data transferred during transaction. 0x00 r/w da t a 7:0 october 01, 2007 310 preliminary inter-integrated circuit (i 2 c) interface
register 4: i 2 c master t imer period (i2cmtpr), offset 0x00c this register specifies the period of the scl clock. i2c master t imer period (i2cmtpr) i2c master 0 base: 0x4002.0000 of fset 0x00c t ype r/w , reset 0x0000.0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 tpr reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 scl clock period this field specifies the period of the scl clock. scl_prd = 2*(1 + tpr)*(scl_lp + scl_hp)*clk_prd where: scl_prd is the scl line period (i 2 c clock). tpr is the t imer period register value (range of 1 to 255). scl_lp is the scl low period (fixed at 6). scl_hp is the scl high period (fixed at 4). 0x1 r/w tpr 7:0 31 1 october 01, 2007 preliminary lm3s600 microcontroller
register 5: i 2 c master interrupt mask (i2cmimr), offset 0x010 this register controls whether a raw interrupt is promoted to a controller interrupt. i2c master interrupt mask (i2cmimr) i2c master 0 base: 0x4002.0000 of fset 0x010 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 im reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 interrupt mask this bit controls whether a raw interrupt is promoted to a controller interrupt. if set, the interrupt is not masked and the interrupt is promoted; otherwise, the interrupt is masked. 0 r/w im 0 october 01, 2007 312 preliminary inter-integrated circuit (i 2 c) interface
register 6: i 2 c master raw interrupt status (i2cmris), offset 0x014 this register specifies whether an interrupt is pending. i2c master raw interrupt status (i2cmris) i2c master 0 base: 0x4002.0000 of fset 0x014 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 ris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 raw interrupt status this bit specifies the raw interrupt state (prior to masking) of the i 2 c master block. if set, an interrupt is pending; otherwise, an interrupt is not pending. 0 ro ris 0 313 october 01, 2007 preliminary lm3s600 microcontroller
register 7: i 2 c master masked interrupt status (i2cmmis), offset 0x018 this register specifies whether an interrupt was signaled. i2c master masked interrupt status (i2cmmis) i2c master 0 base: 0x4002.0000 of fset 0x018 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 mis reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 masked interrupt status this bit specifies the raw interrupt state (after masking) of the i 2 c master block. if set, an interrupt was signaled; otherwise, an interrupt has not been generated since the bit was last cleared. 0 ro mis 0 october 01, 2007 314 preliminary inter-integrated circuit (i 2 c) interface
register 8: i 2 c master interrupt clear (i2cmicr), offset 0x01c this register clears the raw interrupt. i2c master interrupt clear (i2cmicr) i2c master 0 base: 0x4002.0000 of fset 0x01c t ype wo, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 ic reserved wo ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 interrupt clear this bit controls the clearing of the raw interrupt. a write of 1 clears the interrupt; otherwise, a write of 0 has no af fect on the interrupt state. a read of this register returns no meaningful data. 0 wo ic 0 315 october 01, 2007 preliminary lm3s600 microcontroller
register 9: i 2 c master configuration (i2cmcr), offset 0x020 this register configures the mode (master or slave) and sets the interface for test mode loopback. i2c master configuration (i2cmcr) i2c master 0 base: 0x4002.0000 of fset 0x020 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 lpbk reserved mfe sfe reserved r/w ro ro ro r/w r/w ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:6 i 2 c slave function enable this bit specifies whether the interface may operate in slave mode. if set, slave mode is enabled; otherwise, slave mode is disabled. 0 r/w sfe 5 i 2 c master function enable this bit specifies whether the interface may operate in master mode. if set, master mode is enabled; otherwise, master mode is disabled and the interface clock is disabled. 0 r/w mfe 4 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 3:1 i 2 c loopback this bit specifies whether the interface is operating normally or in loopback mode. if set, the device is put in a test mode loopback configuration; otherwise, the device operates normally . 0 r/w lpbk 0 october 01, 2007 316 preliminary inter-integrated circuit (i 2 c) interface
13.6 register descriptions (i2c slave) the remainder of this section lists and describes the i 2 c slave registers, in numerical order by address of fset. see also register descriptions (i 2 c master) on page 304 . 317 october 01, 2007 preliminary lm3s600 microcontroller
register 10: i 2 c slave own address (i2csoar), offset 0x000 this register consists of seven address bits that identify the stellaris ? i 2 c device on the i 2 c bus. i2c slave own address (i2csoar) i2c slave 0 base: 0x4002.0800 of fset 0x000 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 oar reserved r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:7 i 2 c slave own address this field specifies bits a6 through a0 of the slave address. 0x00 r/w oar 6:0 october 01, 2007 318 preliminary inter-integrated circuit (i 2 c) interface
register 1 1: i 2 c slave control/status (i2cscsr), offset 0x004 this register accesses one control bit when written, and three status bits when read. the read-only status register consists of three bits: the fbr , rreq , and treq bits. the first byte received (fbr) bit is set only after the stellaris ? device detects its own slave address and receives the first data byte from the i 2 c master . the receive request (rreq) bit indicates that the stellaris ? i 2 c device has received a data byte from an i 2 c master . read one data byte from the i 2 c slave data (i2csdr) register to clear the rreq bit. the transmit request (treq) bit indicates that the stellaris ? i 2 c device is addressed as a slave t ransmitter . w rite one data byte into the i 2 c slave data (i2csdr) register to clear the treq bit. the write-only control register consists of one bit: the da bit. the da bit enables and disables the stellaris ? i 2 c slave operation. read-only status register i2c slave control/status (i2cscsr) i2c slave 0 base: 0x4002.0800 of fset 0x004 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 rreq treq fbr reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:3 first byte received indicates that the first byte following the slave s own address is received. this bit is only valid when the rreq bit is set, and is automatically cleared when data has been read from the i2csdr register . note: this bit is not used for slave transmit operations. 0 ro fbr 2 t ransmit request this bit specifies the state of the i 2 c slave with regards to outstanding transmit requests. if set, the i 2 c unit has been addressed as a slave transmitter and uses clock stretching to delay the master until data has been written to the i2csdr register . otherwise, there is no outstanding transmit request. 0 ro treq 1 receive request this bit specifies the status of the i 2 c slave with regards to outstanding receive requests. if set, the i 2 c unit has outstanding receive data from the i 2 c master and uses clock stretching to delay the master until the data has been read from the i2csdr register . otherwise, no receive data is outstanding. 0 ro rreq 0 319 october 01, 2007 preliminary lm3s600 microcontroller
w rite-only control register i2c slave control/status (i2cscsr) i2c slave 0 base: 0x4002.0800 of fset 0x004 t ype wo, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 da reserved wo ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 device active 1=enables the i 2 c slave operation. 0=disables the i 2 c slave operation. 0 wo da 0 october 01, 2007 320 preliminary inter-integrated circuit (i 2 c) interface
register 12: i 2 c slave data (i2csdr), offset 0x008 this register contains the data to be transmitted when in the slave t ransmit state, and the data received when in the slave receive state. i2c slave data (i2csdr) i2c slave 0 base: 0x4002.0800 of fset 0x008 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 da t a reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 data for t ransfer this field contains the data for transfer during a slave receive or transmit operation. 0x0 r/w da t a 7:0 321 october 01, 2007 preliminary lm3s600 microcontroller
register 13: i 2 c slave interrupt mask (i2csimr), offset 0x00c this register controls whether a raw interrupt is promoted to a controller interrupt. i2c slave interrupt mask (i2csimr) i2c slave 0 base: 0x4002.0800 of fset 0x00c t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 im reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 interrupt mask this bit controls whether a raw interrupt is promoted to a controller interrupt. if set, the interrupt is not masked and the interrupt is promoted; otherwise, the interrupt is masked. 0 r/w im 0 october 01, 2007 322 preliminary inter-integrated circuit (i 2 c) interface
register 14: i 2 c slave raw interrupt status (i2csris), offset 0x010 this register specifies whether an interrupt is pending. i2c slave raw interrupt status (i2csris) i2c slave 0 base: 0x4002.0800 of fset 0x010 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 ris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 raw interrupt status this bit specifies the raw interrupt state (prior to masking) of the i 2 c slave block. if set, an interrupt is pending; otherwise, an interrupt is not pending. 0 ro ris 0 323 october 01, 2007 preliminary lm3s600 microcontroller
register 15: i 2 c slave masked interrupt status (i2csmis), offset 0x014 this register specifies whether an interrupt was signaled. i2c slave masked interrupt status (i2csmis) i2c slave 0 base: 0x4002.0800 of fset 0x014 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 mis reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 masked interrupt status this bit specifies the raw interrupt state (after masking) of the i 2 c slave block. if set, an interrupt was signaled; otherwise, an interrupt has not been generated since the bit was last cleared. 0 ro mis 0 october 01, 2007 324 preliminary inter-integrated circuit (i 2 c) interface
register 16: i 2 c slave interrupt clear (i2csicr), offset 0x018 this register clears the raw interrupt. i2c slave interrupt clear (i2csicr) i2c slave 0 base: 0x4002.0800 of fset 0x018 t ype wo, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 ic reserved wo ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 clear interrupt this bit controls the clearing of the raw interrupt. a write of 1 clears the interrupt; otherwise a write of 0 has no af fect on the interrupt state. a read of this register returns no meaningful data. 0 wo ic 0 325 october 01, 2007 preliminary lm3s600 microcontroller
14 analog comparators an analog comparator is a peripheral that compares two analog voltages, and provides a logical output that signals the comparison result. the lm3s600 controller provides three independent integrated analog comparators that can be configured to drive an output or generate an interrupt. note: not all comparators have the option to drive an output pin. see the comparator operating mode tables for more information. a comparator can compare a test voltage against any one of these voltages: an individual external reference voltage a shared single external reference voltage a shared internal reference voltage the comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts to cause it to start capturing a sample sequence. october 01, 2007 326 preliminary analog comparators
14.1 block diagram figure 14-1. analog comparator module block diagram 14.2 functional description important: it is recommended that the digital-input enable (the gpioden bit in the gpio module) for the analog input pin be disabled to prevent excessive current draw from the i/o pads. the comparator compares the vin- and vin+ inputs to produce an output, vout . vin- < vin+, vout = 1 vin- > vin+, vout = 0 as shown in figure 14-2 on page 328 , the input source for vin- is an external input. in addition to an external input, input sources for vin+ can be the +ve input of comparator 0 or an internal reference. 327 october 01, 2007 preliminary lm3s600 microcontroller interr upt c2+ c2- output +v e input (alter nate) +v e input interr upt -v e input ref erence input compar ator 2 a cst a t2 a cctl2 interr upt c1- c1+ output +v e input (alter nate) +v e input interr upt -v e input ref erence input compar ator 1 a cst a t1 a cctl1 c1o v oltage ref a crefctl output +v e input (alter nate) +v e input interr upt -v e input ref erence input compar ator 0 a cst a t0 a cctl0 c0+ inter nal b us interr upt c0- c0o c2o
figure 14-2. structure of comparator unit a comparator is configured through two status/control registers ( acctl and acst a t ). the internal reference is configured through one control register ( acrefctl ). interrupt status and control is configured through three registers ( acmis , acris , and acinten ). the operating modes of the comparators are shown in the comparator operating mode tables. t ypically , the comparator output is used internally to generate controller interrupts. it may also be used to drive an external pin. important: certain register bit values must be set before using the analog comparators. the proper pad configuration for the comparator input and output pins are described in the comparator operating mode tables. t able 14-1. comparator 0 operating modes comparator 0 accntl0 interrupt output vin+ vin- asrcp yes c0o c0+ c0- 00 yes c0o c0+ c0- 01 yes c0o v ref c0- 10 yes c0o reserved c0- 1 1 t able 14-2. comparator 1 operating modes comparator 1 accntl1 interrupt output vin+ vin- asrcp yes c1o/c1+ c1o/c1+ a c1- 00 yes c1o/c1+ c0+ c1- 01 yes c1o/c1+ v ref c1- 10 yes c1o/c1+ reserved c1- 1 1 a. c1o and c1+ signals share a single pin and may only be used as one or the other . october 01, 2007 328 preliminary analog comparators output -v e input +v e input interr upt inter nal b us +v e input (alter nate) ref erence input a cst a t a cctl intgen 2 1 0 cinv
t able 14-3. comparator 2 operating modes comparator 2 accntl2 interrupt output vin+ vin- asrcp yes c2o/c2+ c2o/c2+ a c2- 00 yes c2o/c2+ c0+ c2- 01 yes c2o/c2+ v ref c2- 10 yes c2o/c2+ reserved c2- 1 1 a. c2o and c2+ signals share a single pin and may only be used as one or the other . 14.2.1 internal reference programming the structure of the internal reference is shown in figure 14-3 on page 329 . this is controlled by a single configuration register ( acrefctl ). t able 14-4 on page 329 shows the programming options to develop specific internal reference values, to compare an external voltage against a particular voltage generated internally . figure 14-3. comparator internal reference structure t able 14-4. internal reference v oltage and acrefctl field v alues output reference v oltage based on vref field v alue acrefctl register rng bit v alue en bit v alue 0 v (gnd) for any value of vref; however , it is recommended that rng=1 and vref=0 for the least noisy ground reference. rng=x en=0 329 october 01, 2007 preliminary lm3s600 microcontroller 8r r r 8r r r ??? ??? 0 decoder 1 15 14 a vdd en inter nal ref erence vref rng
output reference v oltage based on vref field v alue acrefctl register rng bit v alue en bit v alue t otal resistance in ladder is 32 r. the range of internal reference in this mode is 0.825-2.37 v . rng=0 en=1 t otal resistance in ladder is 24 r. v ref = 0.1375 x v ref the range of internal reference for this mode is 0.0-2.0625 v . rng=1 14.3 initialization and configuration the following example shows how to configure an analog comparator to read back its output value from an internal register . 1. enable the analog comparator 0 clock by writing a value of 0x0010.0000 to the rcgc1 register in the system control module. 2. in the gpio module, enable the gpio port/pin associated with c0- as a gpio input. 3. configure the internal voltage reference to 1.65 v by writing the acrefctl register with the value 0x0000.030c. 4. configure comparator 0 to use the internal voltage reference and to not invert the output on the c0o pin by writing the acctl0 register with the value of 0x0000.040c. 5. delay for some time. 6. read the comparator output value by reading the acst a t0 register s oval value. change the level of the signal input on c0- to see the oval value change. 14.4 register map t able 14-5 on page 331 lists the comparator registers. the of fset listed is a hexadecimal increment to the register s address, relative to the analog comparator base address of 0x4003.c000. october 01, 2007 330 preliminary analog comparators v r e f a v d d r v r e f r t - - - - - - - - - - - - - - - - - = v r e f a v d d v re f 8 + ( ) 3 2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - = v r e f 0 . 8 2 5 0 . 1 0 3 v r e f + = v r e f a v d d r v r e f r t - - - - - - - - - - - - - - - - - = v r e f a v d d v re f ( ) 2 4 - - - - - - - - - - - - - - - - - - - - - =
t able 14-5. analog comparators register map see page description reset t ype name offset 332 analog comparator masked interrupt status 0x0000.0000 r/w1c acmis 0x00 333 analog comparator raw interrupt status 0x0000.0000 ro acris 0x04 334 analog comparator interrupt enable 0x0000.0000 r/w acinten 0x08 335 analog comparator reference v oltage control 0x0000.0000 r/w acrefctl 0x10 336 analog comparator status 0 0x0000.0000 ro acst a t0 0x20 337 analog comparator control 0 0x0000.0000 r/w acctl0 0x24 336 analog comparator status 1 0x0000.0000 ro acst a t1 0x40 337 analog comparator control 1 0x0000.0000 r/w acctl1 0x44 336 analog comparator status 2 0x0000.0000 ro acst a t2 0x60 337 analog comparator control 2 0x0000.0000 r/w acctl2 0x64 14.5 register descriptions the remainder of this section lists and describes the analog comparator registers, in numerical order by address of fset. 331 october 01, 2007 preliminary lm3s600 microcontroller
register 1: analog comparator masked interrupt status (acmis), offset 0x00 this register provides a summary of the interrupt status (masked) of the comparator . analog comparator masked interrupt status (acmis) base 0x4003.c000 of fset 0x00 t ype r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 in0 in1 in2 reserved r/w1c r/w1c r/w1c ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:3 comparator 2 masked interrupt status gives the masked interrupt state of this interrupt. w rite 1 to this bit to clear the pending interrupt. 0 r/w1c in2 2 comparator 1 masked interrupt status gives the masked interrupt state of this interrupt. w rite 1 to this bit to clear the pending interrupt. 0 r/w1c in1 1 comparator 0 masked interrupt status gives the masked interrupt state of this interrupt. w rite 1 to this bit to clear the pending interrupt. 0 r/w1c in0 0 october 01, 2007 332 preliminary analog comparators
register 2: analog comparator raw interrupt status (acris), offset 0x04 this register provides a summary of the interrupt status (raw) of the comparator . analog comparator raw interrupt status (acris) base 0x4003.c000 of fset 0x04 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 in0 in1 in2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:3 comparator 2 interrupt status when set, indicates that an interrupt has been generated by comparator 2. 0 ro in2 2 comparator 1 interrupt status when set, indicates that an interrupt has been generated by comparator 1. 0 ro in1 1 comparator 0 interrupt status when set, indicates that an interrupt has been generated by comparator 0. 0 ro in0 0 333 october 01, 2007 preliminary lm3s600 microcontroller
register 3: analog comparator interrupt enable (acinten), offset 0x08 this register provides the interrupt enable for the comparator . analog comparator interrupt enable (acinten) base 0x4003.c000 of fset 0x08 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 in0 in1 in2 reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:3 comparator 2 interrupt enable when set, enables the controller interrupt from the comparator 2 output 0 r/w in2 2 comparator 1 interrupt enable when set, enables the controller interrupt from the comparator 1 output. 0 r/w in1 1 comparator 0 interrupt enable when set, enables the controller interrupt from the comparator 0 output. 0 r/w in0 0 october 01, 2007 334 preliminary analog comparators
register 4: analog comparator reference v oltage control (acrefctl), offset 0x10 this register specifies whether the resistor ladder is powered on as well as the range and tap. analog comparator reference v oltage control (acrefctl) base 0x4003.c000 of fset 0x10 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 vref reserved rng en reserved r/w r/w r/w r/w ro ro ro ro r/w r/w ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:10 resistor ladder enable the en bit specifies whether the resistor ladder is powered on. if 0, the resistor ladder is unpowered. if 1, the resistor ladder is connected to the analog v dd . this bit is reset to 0 so that the internal reference consumes the least amount of power if not used and programmed. 0 r/w en 9 resistor ladder range the rng bit specifies the range of the resistor ladder . if 0, the resistor ladder has a total resistance of 32 r. if 1, the resistor ladder has a total resistance of 24 r. 0 r/w rng 8 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 7:4 resistor ladder v oltage ref the vref bit field specifies the resistor ladder tap that is passed through an analog multiplexer . the voltage corresponding to the tap position is the internal reference voltage available for comparison. see t able 14-4 on page 329 for some output reference voltage examples. 0x00 r/w vref 3:0 335 october 01, 2007 preliminary lm3s600 microcontroller
register 5: analog comparator status 0 (acst a t0), offset 0x20 register 6: analog comparator status 1 (acst a t1), offset 0x40 register 7: analog comparator status 2 (acst a t2), offset 0x60 these registers specify the current output value of the comparator . analog comparator status 0 (acst a t0) base 0x4003.c000 of fset 0x20 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved ov al reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:2 comparator output v alue the oval bit specifies the current output value of the comparator . 0 ro ov al 1 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 0 october 01, 2007 336 preliminary analog comparators
register 8: analog comparator control 0 (acctl0), offset 0x24 register 9: analog comparator control 1 (acctl1), offset 0x44 register 10: analog comparator control 2 (acctl2), offset 0x64 these registers configure the comparator s input and output. analog comparator control 0 (acctl0) base 0x4003.c000 of fset 0x24 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved cinv isen isl v al reserved asrcp reserved ro r/w r/w r/w r/w ro ro ro ro r/w r/w ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 1 analog source positive the asrcp field specifies the source of input voltage to the vin+ terminal of the comparator . the encodings for this field are as follows: function v alue pin value 0x0 pin value of c0+ 0x1 internal voltage reference 0x2 reserved 0x3 0x00 r/w asrcp 10:9 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 8:5 interrupt sense level v alue the islval bit specifies the sense value of the input that generates an interrupt if in level sense mode. if 0, an interrupt is generated if the comparator output is low . otherwise, an interrupt is generated if the comparator output is high. 0 r/w isl v al 4 337 october 01, 2007 preliminary lm3s600 microcontroller
description reset t ype name bit/field interrupt sense the isen field specifies the sense of the comparator output that generates an interrupt. the sense conditioning is as follows: function v alue level sense, see islval 0x0 falling edge 0x1 rising edge 0x2 either edge 0x3 0x0 r/w isen 3:2 comparator output invert the cinv bit conditionally inverts the output of the comparator . if 0, the output of the comparator is unchanged. if 1, the output of the comparator is inverted prior to being processed by hardware. 0 r/w cinv 1 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 0 october 01, 2007 338 preliminary analog comparators
15 pin diagram figure 15-1 on page 339 shows the pin diagram and pin-to-signal-name mapping. figure 15-1. pin connection diagram 339 october 01, 2007 preliminary lm3s600 microcontroller lm3s600 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 pe5 / ccp5 pe4 / ccp3 pe3 / ccp1 pe2 / ccp4 rst ldo vdd gnd osc0 osc1 pc7 / c2- pc6 / c2+ / c2o pc5 / c1+ / c1o pc4 vdd gnd p a0 / u0rx p a1 / u0tx p a2 / ssiclk p a3 / ssifss p a4 / ssirx p a5 / ssitx vdd gnd pd0 pd1 pd2 / u1rx pd3 / u1tx pb0 pb1 gnd vdd pb2 / i2cscl pb3 / i2csd a pe0 pe1 pc3 / tdo / sw o pc2 / tdi pc1 / tms / swdio pc0 / tck / swclk pb7 / trst pb6 / c0+ pb5 / c1- pb4 / c0- pd4 / ccp0 pd5 / ccp2 pd6 pd7 / c0o
16 signal t ables the following tables list the signals available for each pin. functionality is enabled by software with the gpioafsel register . important: all multiplexed pins are gpios by default, with the exception of the five jt ag pins ( pb7 and pc[3:0] ) which default to the jt ag functionality . t able 16-1 on page 340 shows the pin-to-signal-name mapping, including functional characteristics of the signals. t able 16-2 on page 342 lists the signals in alphabetical order by signal name. t able 16-3 on page 344 groups the signals by functionality , except for gpios. t able 16-4 on page 345 lists the gpio pins and their alternate functionality . t able 16-1. signals by pin number description buffer t ype pin t ype pin name pin number gpio port e bit 5 ttl i/o pe5 1 capture/compare/pwm 5 ttl i/o ccp5 gpio port e bit 4 ttl i/o pe4 2 capture/compare/pwm 3 ttl i/o ccp3 gpio port e bit 3 ttl i/o pe3 3 capture/compare/pwm 1 ttl i/o ccp1 gpio port e bit 2 ttl i/o pe2 4 capture/compare/pwm 4 ttl i/o ccp4 system reset input. ttl i rst 5 low drop-out regulator output voltage. this pin requires an external capacitor between the pin and gnd of 1 f or greater . power - ldo 6 positive supply for i/o and some logic. power - vdd 7 ground reference for logic and i/o pins. power - gnd 8 main oscillator crystal input or an external clock reference input. analog i osc0 9 main oscillator crystal output. analog o osc1 10 gpio port c bit 7 ttl i/o pc7 1 1 analog comparator 2 negative input analog i c2- gpio port c bit 6 ttl i/o pc6 12 analog comparator positive input analog i c2+ analog comparator 2 output ttl o c2o gpio port c bit 5 ttl i/o pc5 13 analog comparator positive input analog i c1+ analog comparator 1 output ttl o c1o gpio port c bit 4 ttl i/o pc4 14 positive supply for i/o and some logic. power - vdd 15 ground reference for logic and i/o pins. power - gnd 16 gpio port a bit 0 ttl i/o pa0 17 uar t module 0 receive ttl i u0rx october 01, 2007 340 preliminary signal t ables
description buffer t ype pin t ype pin name pin number gpio port a bit 1 ttl i/o pa1 18 uar t module 0 transmit ttl o u0tx gpio port a bit 2 ttl i/o pa2 19 ssi clock ttl i/o ssiclk gpio port a bit 3 ttl i/o pa3 20 ssi frame ttl i/o ssifss gpio port a bit 4 ttl i/o pa4 21 ssi module 0 receive ttl i ssirx gpio port a bit 5 ttl i/o pa5 22 ssi module 0 transmit ttl o ssitx positive supply for i/o and some logic. power - vdd 23 ground reference for logic and i/o pins. power - gnd 24 gpio port d bit 0 ttl i/o pd0 25 gpio port d bit 1 ttl i/o pd1 26 gpio port d bit 2 ttl i/o pd2 27 uar t module 1 receive. when in irda mode, this signal has irda modulation. ttl i u1rx gpio port d bit 3 ttl i/o pd3 28 uar t module 1 transmit. when in irda mode, this signal has irda modulation. ttl o u1tx gpio port b bit 0 ttl i/o pb0 29 gpio port b bit 1 ttl i/o pb1 30 ground reference for logic and i/o pins. power - gnd 31 positive supply for i/o and some logic. power - vdd 32 gpio port b bit 2 ttl i/o pb2 33 i2c module 0 clock od i/o i2cscl gpio port b bit 3 ttl i/o pb3 34 i2c module 0 data od i/o i2csda gpio port e bit 0 ttl i/o pe0 35 gpio port e bit 1 ttl i/o pe1 36 gpio port c bit 3 ttl i/o pc3 37 jt ag tdo and swo ttl o tdo jt ag tdo and swo ttl o swo gpio port c bit 2 ttl i/o pc2 38 jt ag tdi ttl i tdi gpio port c bit 1 ttl i/o pc1 39 jt ag tms and swdio ttl i/o tms jt ag tms and swdio ttl i/o swdio gpio port c bit 0 ttl i/o pc0 40 jt ag/swd clk ttl i tck jt ag/swd clk ttl i swclk gpio port b bit 7 ttl i/o pb7 41 jt ag trstn ttl i trst 341 october 01, 2007 preliminary lm3s600 microcontroller
description buffer t ype pin t ype pin name pin number gpio port b bit 6 ttl i/o pb6 42 analog comparator 0 positive input analog i c0+ gpio port b bit 5 ttl i/o pb5 43 analog comparator 1 negative input analog i c1- gpio port b bit 4 ttl i/o pb4 44 analog comparator 0 negative input analog i c0- gpio port d bit 4 ttl i/o pd4 45 capture/compare/pwm 0 ttl i/o ccp0 gpio port d bit 5 ttl i/o pd5 46 capture/compare/pwm 2 ttl i/o ccp2 gpio port d bit 6 ttl i/o pd6 47 gpio port d bit 7 ttl i/o pd7 48 analog comparator 0 output ttl o c0o t able 16-2. signals by signal name description buffer t ype pin t ype pin number pin name analog comparator 0 positive input analog i 42 c0+ analog comparator 0 negative input analog i 44 c0- analog comparator 0 output ttl o 48 c0o analog comparator positive input analog i 13 c1+ analog comparator 1 negative input analog i 43 c1- analog comparator 1 output ttl o 13 c1o analog comparator positive input analog i 12 c2+ analog comparator 2 negative input analog i 1 1 c2- analog comparator 2 output ttl o 12 c2o capture/compare/pwm 0 ttl i/o 45 ccp0 capture/compare/pwm 1 ttl i/o 3 ccp1 capture/compare/pwm 2 ttl i/o 46 ccp2 capture/compare/pwm 3 ttl i/o 2 ccp3 capture/compare/pwm 4 ttl i/o 4 ccp4 capture/compare/pwm 5 ttl i/o 1 ccp5 ground reference for logic and i/o pins. power - 8 gnd ground reference for logic and i/o pins. power - 16 gnd ground reference for logic and i/o pins. power - 24 gnd ground reference for logic and i/o pins. power - 31 gnd i2c module 0 clock od i/o 33 i2cscl i2c module 0 data od i/o 34 i2csda low drop-out regulator output voltage. this pin requires an external capacitor between the pin and gnd of 1 f or greater . power - 6 ldo main oscillator crystal input or an external clock reference input. analog i 9 osc0 main oscillator crystal output. analog o 10 osc1 october 01, 2007 342 preliminary signal t ables
description buffer t ype pin t ype pin number pin name gpio port a bit 0 ttl i/o 17 pa0 gpio port a bit 1 ttl i/o 18 pa1 gpio port a bit 2 ttl i/o 19 pa2 gpio port a bit 3 ttl i/o 20 pa3 gpio port a bit 4 ttl i/o 21 pa4 gpio port a bit 5 ttl i/o 22 pa5 gpio port b bit 0 ttl i/o 29 pb0 gpio port b bit 1 ttl i/o 30 pb1 gpio port b bit 2 ttl i/o 33 pb2 gpio port b bit 3 ttl i/o 34 pb3 gpio port b bit 4 ttl i/o 44 pb4 gpio port b bit 5 ttl i/o 43 pb5 gpio port b bit 6 ttl i/o 42 pb6 gpio port b bit 7 ttl i/o 41 pb7 gpio port c bit 0 ttl i/o 40 pc0 gpio port c bit 1 ttl i/o 39 pc1 gpio port c bit 2 ttl i/o 38 pc2 gpio port c bit 3 ttl i/o 37 pc3 gpio port c bit 4 ttl i/o 14 pc4 gpio port c bit 5 ttl i/o 13 pc5 gpio port c bit 6 ttl i/o 12 pc6 gpio port c bit 7 ttl i/o 1 1 pc7 gpio port d bit 0 ttl i/o 25 pd0 gpio port d bit 1 ttl i/o 26 pd1 gpio port d bit 2 ttl i/o 27 pd2 gpio port d bit 3 ttl i/o 28 pd3 gpio port d bit 4 ttl i/o 45 pd4 gpio port d bit 5 ttl i/o 46 pd5 gpio port d bit 6 ttl i/o 47 pd6 gpio port d bit 7 ttl i/o 48 pd7 gpio port e bit 0 ttl i/o 35 pe0 gpio port e bit 1 ttl i/o 36 pe1 gpio port e bit 2 ttl i/o 4 pe2 gpio port e bit 3 ttl i/o 3 pe3 gpio port e bit 4 ttl i/o 2 pe4 gpio port e bit 5 ttl i/o 1 pe5 system reset input. ttl i 5 rst ssi clock ttl i/o 19 ssiclk ssi frame ttl i/o 20 ssifss ssi module 0 receive ttl i 21 ssirx ssi module 0 transmit ttl o 22 ssitx jt ag/swd clk ttl i 40 swclk 343 october 01, 2007 preliminary lm3s600 microcontroller
description buffer t ype pin t ype pin number pin name jt ag tms and swdio ttl i/o 39 swdio jt ag tdo and swo ttl o 37 swo jt ag/swd clk ttl i 40 tck jt ag tdi ttl i 38 tdi jt ag tdo and swo ttl o 37 tdo jt ag tms and swdio ttl i/o 39 tms jt ag trstn ttl i 41 trst uar t module 0 receive ttl i 17 u0rx uar t module 0 transmit ttl o 18 u0tx uar t module 1 receive. when in irda mode, this signal has irda modulation. ttl i 27 u1rx uar t module 1 transmit. when in irda mode, this signal has irda modulation. ttl o 28 u1tx positive supply for i/o and some logic. power - 7 vdd positive supply for i/o and some logic. power - 15 vdd positive supply for i/o and some logic. power - 23 vdd positive supply for i/o and some logic. power - 32 vdd t able 16-3. signals by function, except for gpio description buffer t ype pin t ype pin number pin name function analog comparator 0 positive input analog i 42 c0+ analog comparators analog comparator 0 negative input analog i 44 c0- analog comparator 0 output ttl o 48 c0o analog comparator positive input analog i 13 c1+ analog comparator 1 negative input analog i 43 c1- analog comparator 1 output ttl o 13 c1o analog comparator positive input analog i 12 c2+ analog comparator 2 negative input analog i 1 1 c2- analog comparator 2 output ttl o 12 c2o capture/compare/pwm 0 ttl i/o 45 ccp0 general-purpose t imers capture/compare/pwm 1 ttl i/o 3 ccp1 capture/compare/pwm 2 ttl i/o 46 ccp2 capture/compare/pwm 3 ttl i/o 2 ccp3 capture/compare/pwm 4 ttl i/o 4 ccp4 capture/compare/pwm 5 ttl i/o 1 ccp5 i2c module 0 clock od i/o 33 i2cscl i2c i2c module 0 data od i/o 34 i2csda october 01, 2007 344 preliminary signal t ables
description buffer t ype pin t ype pin number pin name function jt ag/swd clk ttl i 40 swclk jt ag/swd/swo jt ag tms and swdio ttl i/o 39 swdio jt ag tdo and swo ttl o 37 swo jt ag/swd clk ttl i 40 tck jt ag tdi ttl i 38 tdi jt ag tdo and swo ttl o 37 tdo jt ag tms and swdio ttl i/o 39 tms ground reference for logic and i/o pins. power - 8 gnd power ground reference for logic and i/o pins. power - 16 gnd ground reference for logic and i/o pins. power - 24 gnd ground reference for logic and i/o pins. power - 31 gnd low drop-out regulator output voltage. this pin requires an external capacitor between the pin and gnd of 1 f or greater . power - 6 ldo positive supply for i/o and some logic. power - 7 vdd positive supply for i/o and some logic. power - 15 vdd positive supply for i/o and some logic. power - 23 vdd positive supply for i/o and some logic. power - 32 vdd ssi clock ttl i/o 19 ssiclk ssi ssi frame ttl i/o 20 ssifss ssi module 0 receive ttl i 21 ssirx ssi module 0 transmit ttl o 22 ssitx main oscillator crystal input or an external clock reference input. analog i 9 osc0 system control & clocks main oscillator crystal output. analog o 10 osc1 system reset input. ttl i 5 rst jt ag trstn ttl i 41 trst uar t module 0 receive ttl i 17 u0rx uar t uar t module 0 transmit ttl o 18 u0tx uar t module 1 receive. when in irda mode, this signal has irda modulation. ttl i 27 u1rx uar t module 1 transmit. when in irda mode, this signal has irda modulation. ttl o 28 u1tx t able 16-4. gpio pins and alternate functions multiplexed function multiplexed function pin number gpio pin u0rx 17 pa0 u0tx 18 pa1 ssiclk 19 pa2 ssifss 20 pa3 ssirx 21 pa4 ssitx 22 pa5 29 pb0 345 october 01, 2007 preliminary lm3s600 microcontroller
multiplexed function multiplexed function pin number gpio pin 30 pb1 i2cscl 33 pb2 i2csda 34 pb3 c0- 44 pb4 c1- 43 pb5 c0+ 42 pb6 trst 41 pb7 swclk tck 40 pc0 swdio tms 39 pc1 tdi 38 pc2 swo tdo 37 pc3 14 pc4 c1o c1+ 13 pc5 c2o c2+ 12 pc6 c2- 1 1 pc7 25 pd0 26 pd1 u1rx 27 pd2 u1tx 28 pd3 ccp0 45 pd4 ccp2 46 pd5 47 pd6 c0o 48 pd7 35 pe0 36 pe1 ccp4 4 pe2 ccp1 3 pe3 ccp3 2 pe4 ccp5 1 pe5 october 01, 2007 346 preliminary signal t ables
17 operating characteristics t able 17-1. t emperature characteristics unit v alue symbol characteristic c -40 to +85 t a operating temperature range a a. maximum storage temperature is 150c. t able 17-2. thermal characteristics unit v alue symbol characteristic c/w 76 ja thermal resistance (junction to ambient) a c t a + (p a vg ? ja ) t j a verage junction temperature b c 1 15 c t jmax maximum junction temperature a. junction to ambient thermal resistance ja numbers are determined by a package simulator . b. power dissipation is a function of temperature. c. t jmax calculation is based on power consumption values and conditions as specified in power specifications on page 383 of the data sheet. 347 october 01, 2007 preliminary lm3s600 microcontroller
18 electrical characteristics 18.1 dc characteristics 18.1.1 maximum ratings the maximum ratings are the limits to which the device can be subjected without permanently damaging the device. note: the device is not guaranteed to operate properly at the maximum ratings. t able 18-1. maximum ratings unit v alue symbol characteristic a v 0.0 to +3.6 v dd supply voltage range (v dd ) v -0.3 to 5.5 v in input voltage ma 100 i maximum current for pins, excluding pins operating as gpios ma 100 i maximum current for gpio pins a. v oltages are measured with respect to gnd. important: this device contains circuitry to protect the inputs against damage due to high-static voltages or electric fields; however , it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either gnd or v dd ). 18.1.2 recommended dc operating conditions t able 18-2. recommended dc operating conditions unit max nom min parameter name parameter v 3.6 3.3 3.0 supply voltage v dd v 5.0 - 2.0 high-level input voltage v ih v 1.3 - -0.3 low-level input voltage v il v v dd - 0.8 * v dd high-level input voltage for schmitt trigger inputs v sih v 0.2 * v dd - 0 low-level input voltage for schmitt trigger inputs v sil v - - 2.4 high-level output voltage v oh v 0.4 - - low-level output voltage v ol high-level source current, v oh =2.4 v i oh ma - - 2.0 2-ma drive ma - - 4.0 4-ma drive ma - - 8.0 8-ma drive low-level sink current, v ol =0.4 v i ol ma - - 2.0 2-ma drive ma - - 4.0 4-ma drive ma - - 8.0 8-ma drive october 01, 2007 348 preliminary electrical characteristics
18.1.3 on-chip low drop-out (ldo) regulator characteristics t able 18-3. ldo regulator characteristics unit max nom min parameter name parameter v 2.75 2.25 programmable internal (logic) power supply output value v ldoout % - 2% - output voltage accuracy s 100 - - power-on time t pon s 200 - - t ime on t on s 100 - - t ime of f t off mv - 50 - step programming incremental voltage v step f 3.0 - 1.0 external filter capacitor size for internal power supply c ldo 18.1.4 power specifications the power measurements specified in the tables that follow are run on the core processor using sram with the following specifications (except as noted): v dd = 3.3 v t emperature = 25c t able 18-4. detailed power specifications unit max nom conditions parameter name parameter ma 1 10 95 ldo = 2.50 v code = while(1){} executed in flash peripherals = all clock-gated on system clock = 50 mhz (with pll) run mode 1 (flash loop) i dd_run ma 75 60 ldo = 2.50 v code = while(1){} executed in flash peripherals = all clock-gated off system clock = 50 mhz (with pll) run mode 2 (flash loop) ma 95 85 ldo = 2.50 v code = while(1){} executed in sram peripherals = all clock-gated on system clock = 50 mhz (with pll) run mode 1 (sram loop) ma 60 50 ldo = 2.50 v code = while(1){} executed in sram peripherals = all clock-gated off system clock = 50 mhz (with pll) run mode 2 (sram loop) ma 22 19 ldo = 2.50 v peripherals = all clock-gated off system clock = 50 mhz (with pll) sleep mode i dd_sleep 349 october 01, 2007 preliminary lm3s600 microcontroller
unit max nom conditions parameter name parameter a 1 150 950 ldo = 2.25 v peripherals = all off system clock = mosc/16 deep-sleep mode i dd_deepsleep 18.1.5 flash memory characteristics t able 18-5. flash memory characteristics unit max nom min parameter name parameter cycles - - 1000 number of guaranteed program/erase cycles before failure a pe cyc years - - 10 data retention at average operating temperature of 85?c t ret s - - 20 w ord program time t prog ms - - 20 page erase time t erase ms - - 200 mass erase time t me a. a program/erase cycle is defined as switching the bits from 1-> 0 -> 1. 18.2 ac characteristics 18.2.1 load conditions unless otherwise specified, the following conditions are true for all timing measurements. t iming measurements are for 4-ma drive strength. figure 18-1. load conditions 18.2.2 clocks t able 18-6. phase locked loop (pll) characteristics unit max nom min parameter name parameter mhz 8.192 - 3.579545 crystal reference a f ref_crystal mhz 8.192 - 3.579545 external clock reference a f ref_ext mhz - 200 - pll frequency b f pll ms 0.5 - - pll lock time t ready a. the exact value is determined by the crystal value programmed into the xtal field of the run-mode clock configuration (rcc) register . b. pll frequency is automatically calculated by the hardware based on the xtal field of the rcc register . t able 18-7. clock characteristics unit max nom min parameter name parameter mhz 22 12 7 internal oscillator frequency f iosc october 01, 2007 350 preliminary electrical characteristics c l = 50 pf gnd pin
unit max nom min parameter name parameter mhz 8 - 1 main oscillator frequency f mosc ns 1000 - 125 main oscillator period t mosc_per mhz 8 - 1 crystal reference using the main oscillator (pll in byp ass mode) f ref_crystal_bypass mhz 50 - 0 external clock reference (pll in byp ass mode) f ref_ext_bypass mhz 50 - 0 system clock f system_clock 18.2.3 analog comparator t able 18-8. analog comparator characteristics unit max nom min parameter name parameter mv 25 10 - input of fset voltage v os v v dd -1.5 - 0 input common mode voltage range v cm db - - 50 common mode rejection ratio c mrr s 1 - - response time t r t s 10 - - comparator mode change to output v alid t mc t able 18-9. analog comparator v oltage reference characteristics unit max nom min parameter name parameter lsb - v dd /32 - resolution high range r hr lsb - v dd /24 - resolution low range r lr lsb 1/2 - - absolute accuracy high range a hr lsb 1/4 - - absolute accuracy low range a lr 18.2.4 i 2 c t able 18-10. i 2 c characteristics unit max nom min parameter name parameter parameter no. system clocks - - 36 start condition hold time t sch i1 a system clocks - - 36 clock low period t lp i2 a ns (see note b) - - i2cscl / i2csda rise time (v il =0.5 v to v ih =2.4 v) t sr t i3 b system clocks - - 2 data hold time t dh i4 a ns 10 9 - i2cscl / i2csda fall time (v ih =2.4 v to v il =0.5 v) t sft i5 c system clocks - - 24 clock high time t ht i6 a system clocks - - 18 data setup time t ds i7 a system clocks - - 36 start condition setup time (for repeated start condition only) t scsr i8 a system clocks - - 24 stop condition setup time t scs i9 a a. v alues depend on the value programmed into the tpr bit in the i 2 c master t imer period (i2cmtpr) register; a tpr programmed for the maximum i2cscl frequency (tpr=0x2) results in a minimum output timing as shown in the table above. the i 2 c interface is designed to scale the actual data transition time to move it to the middle of the i2cscl low period. the actual position is af fected by the value programmed into the tpr ; however , the numbers given in the above values are minimum values. b. because i2cscl and i2csda are open-drain-type outputs, which the controller can only actively drive low , the time i2cscl or i2csda takes to reach a high level depends on external signal capacitance and pull-up resistor values. c. specified at a nominal 50 pf load. 351 october 01, 2007 preliminary lm3s600 microcontroller
figure 18-2. i 2 c t iming 18.2.5 synchronous serial interface (ssi) t able 18-1 1. ssi characteristics unit max nom min parameter name parameter parameter no. system clocks 65024 - 2 ssiclk cycle time t clk_per s1 t clk_per - 1/2 - ssiclk high time t clk_high s2 t clk_per - 1/2 - ssiclk low time t clk_low s3 ns 26 7.4 - ssiclk rise/fall time t clkrf s4 ns 20 - 0 data from master valid delay time t dmd s5 ns - - 20 data from master setup time t dms s6 ns - - 40 data from master hold time t dmh s7 ns - - 20 data from slave setup time t dss s8 ns - - 40 data from slave hold time t dsh s9 figure 18-3. ssi t iming for ti frame format (frf=01), single t ransfer t iming measurement october 01, 2007 352 preliminary electrical characteristics i2cscl i2csda i1 i2 i4 i6 i7 i8 i5 i3 i9 ssiclk ssifss ssitx ssirx msb lsb s2 s3 s1 s4 4 to 16 bits
figure 18-4. ssi t iming for microwire frame format (frf=10), single t ransfer figure 18-5. ssi t iming for spi frame format (frf=00), with sph=1 18.2.6 jt ag and boundary scan t able 18-12. jt ag characteristics unit max nom min parameter name parameter parameter no. mhz 10 - 0 tck operational clock frequency f tck j1 ns - - 100 tck operational clock period t tck j2 ns - t tck - tck clock low time t tck_low j3 353 october 01, 2007 preliminary lm3s600 microcontroller 0 ssiclk ssifss ssitx ssirx msb lsb msb lsb s2 s3 s1 8-bit control 4 to 16 bits output data ssiclk ( spo=1) ssitx ( master) ssirx ( slave) lsb ssiclk ( spo=0) s2 s1 s4 ssifss lsb s3 msb s5 s6 s7 s9 s8 msb
unit max nom min parameter name parameter parameter no. ns - t tck - tck clock high time t tck_high j4 ns 10 - 0 tck rise time t tck_r j5 ns 10 - 0 tck fall time t tck_f j6 ns - - 20 tms setup time to tck rise t tms_su j7 ns - - 20 tms hold time from tck rise t tms_hld j8 ns - - 25 tdi setup time to tck rise t tdi_su j9 ns - - 25 tdi hold time from tck rise t tdi_hld j10 ns 35 23 - 2-ma drive tck fall to data v alid from high-z j1 1 t tdo_zdv ns 26 15 4-ma drive ns 25 14 8-ma drive ns 29 18 8-ma drive with slew rate control ns 35 21 - 2-ma drive tck fall to data v alid from data v alid j12 t tdo_dv ns 25 14 4-ma drive ns 24 13 8-ma drive ns 28 18 8-ma drive with slew rate control ns 1 1 9 - 2-ma drive tck fall to high-z from data v alid j13 t tdo_dvz ns 9 7 4-ma drive ns 8 6 8-ma drive ns 9 7 8-ma drive with slew rate control ns - - 100 trst assertion time t trst j14 ns - - 10 trst setup time to tck rise t trst_su j15 figure 18-6. jt ag t est clock input t iming october 01, 2007 354 preliminary electrical characteristics tck j6 j5 j3 j4 j2
figure 18-7. jt ag t est access port (t ap) t iming figure 18-8. jt ag trst t iming 18.2.7 general-purpose i/o note: all gpios are 5 v-tolerant. t able 18-13. gpio characteristics unit max nom min condition parameter name parameter ns 26 17 - 2-ma drive gpio rise t ime (from 20% to 80% of v dd ) t gpior ns 13 9 4-ma drive ns 9 6 8-ma drive ns 12 10 8-ma drive with slew rate control ns 25 17 - 2-ma drive gpio fall t ime (from 80% to 20% of v dd ) t gpiof ns 12 8 4-ma drive ns 10 6 8-ma drive ns 13 1 1 8-ma drive with slew rate control 18.2.8 reset t able 18-14. reset characteristics unit max nom min parameter name parameter parameter no. v - 2.0 - reset threshold v th r1 355 october 01, 2007 preliminary lm3s600 microcontroller tdo output v alid tck tdo output v alid j12 tdo tdi tms tdi input v alid tdi input v alid j13 j9 j10 tms input v alid j9 j10 tms input v alid j1 1 j7 j8 j8 j7 tck j14 j15 trst
unit max nom min parameter name parameter parameter no. v 2.95 2.9 2.85 brown-out threshold v bth r2 ms - 10 - power-on reset timeout t por r3 s - 500 - brown-out timeout t bor r4 ms 30 - 15 internal reset timeout after por t irpor r5 s 20 - 2.5 internal reset timeout after bor a t irbor r6 ms 30 - 15 internal reset timeout after hardware reset ( rst pin) t irhwr r7 s 20 - 2.5 internal reset timeout after software-initiated system reset a t irswr r8 s 20 - 2.5 internal reset timeout after watchdog reset a t ir wdr r9 s 20 - 2.5 internal reset timeout after ldo reset a t irldor r10 ms 100 - - supply voltage (v dd ) rise time (0 v-3.3 v) t vddrise r1 1 a. 20 * t mosc_per figure 18-9. external reset t iming ( rst ) figure 18-10. power-on reset t iming october 01, 2007 356 preliminary electrical characteristics rst /reset ( internal) r7 vdd /por ( internal) /reset ( internal) r3 r1 r5
figure 18-1 1. brown-out reset t iming figure 18-12. software reset t iming figure 18-13. w atchdog reset t iming figure 18-14. ldo reset t iming 357 october 01, 2007 preliminary lm3s600 microcontroller vdd /bor ( internal) /reset ( internal) r2 r4 r6 r8 sw reset /reset ( internal) wdog reset ( internal) /reset ( internal) r9 ldo reset ( internal) /reset ( internal) r10
19 package information figure 19-1. 48-pin lqfp package note: the following notes apply to the package drawing. 1. all dimensions are in mm. all dimensioning and tolerancing conform to ansi y14.5m-1982. 2. the top package body size may be smaller than the bottom package body size by as much as 0.20. 3. datums a-b and -d- to be determined at datum plane -h-. 4. t o be determined at seating plane -c-. 5. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. 6. surface finish of the package is #24-27 charmille (1.6-2.3mr0) pin 1 and ejector pin may be less than 0.1mr0. october 01, 2007 358 preliminary package information ccc aaa b b b
7. dambar removal protrusion does not exceed 0.08. intrusion does not exceed 0.03. 8. burr does not exceed 0.08 in any direction. 9. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08. dambar cannot be located on the lower radius or the foot. minimum space between protrusion and adjacent lead is 0.07 for 0.40 and 0.50 pitch package. 10. corner radius of plastic body does not exceed 0.20. 1 1. these dimensions apply to the flat section of the lead between 0.10 and 0.25 from the lead tip. 12. a1 is defined as the distance from the seating plane to the lowest point of the package body . 13. finish of leads is tin plated. 14. all specifications and dimensions are subjected to ip acs manufacturing process flow and materials. 15. m5-026a. where discrepancies between the jedec and ip ac documents exist, this drawing will take the precedence. note package t ype symbol 48ld lqfp max nom min 1.60 === === a 0.15 === 0.05 a 1 1.45 1.40 1.35 a 2 9.00 bsc d 7.00 bsc d 1 9.00 bsc e 7.00 bsc e 1 0.75 0.80 0.45 l 0.50 bsc e 0.27 0.22 0.17 b 0.23 0.20 0.17 b1 0.20 === 0.09 c 0.16 === 0.09 c1 t olerances of form and position 0.20 aaa 0.20 bbb 0.08 ccc 0.08 ddd 359 october 01, 2007 preliminary lm3s600 microcontroller
a serial flash loader a.1 serial flash loader the stellaris ? serial flash loader is a preprogrammed flash-resident utility used to download code to the flash memory of a device without the use of a debug interface. the serial flash loader uses a simple packet interface to provide synchronous communication with the device. the flash loader runs of f the crystal and does not enable the pll, so its speed is determined by the crystal used. the two serial interfaces that can be used are the uar t0 and ssi0 interfaces. for simplicity , both the data format and communication protocol are identical for both serial interfaces. a.2 interfaces once communication with the flash loader is established via one of the serial interfaces, that interface is used until the flash loader is reset or new code takes over . for example, once you start communicating using the ssi port, communications with the flash loader via the uar t are disabled until the device is reset. a.2.1 uart the universal asynchronous receivers/t ransmitters (uar t) communication uses a fixed serial format of 8 bits of data, no parity , and 1 stop bit. the baud rate used for communication is automatically detected by the flash loader and can be any valid baud rate supported by the host and the device. the auto detection sequence requires that the baud rate should be no more than 1/32 the crystal frequency of the board that is running the serial flash loader . this is actually the same as the hardware limitation for the maximum baud rate for any uar t on a stellaris ? device which is calculated as follows: max baud rate = system clock frequency / 16 in order to determine the baud rate, the serial flash loader needs to determine the relationship between its own crystal frequency and the baud rate. this is enough information for the flash loader to configure its uar t to the same baud rate as the host. this automatic baud-rate detection allows the host to use any valid baud rate that it wants to communicate with the device. the method used to perform this automatic synchronization relies on the host sending the flash loader two bytes that are both 0x55. this generates a series of pulses to the flash loader that it can use to calculate the ratios needed to program the uar t to match the host s baud rate. after the host sends the pattern, it attempts to read back one byte of data from the uar t . the flash loader returns the value of 0xcc to indicate successful detection of the baud rate. if this byte is not received after at least twice the time required to transfer the two bytes, the host can resend another pattern of 0x55, 0x55, and wait for the 0xcc byte again until the flash loader acknowledges that it has received a synchronization pattern correctly . for example, the time to wait for data back from the flash loader should be calculated as at least 2*(20(bits/sync)/baud rate (bits/sec)). for a baud rate of 1 15200, this time is 2*(20/1 15200) or 0.35 ms. a.2.2 ssi the synchronous serial interface (ssi) port also uses a fixed serial format for communications, with the framing defined as motorola format with sph set to 1 and spo set to 1. see frame formats on page 256 in the ssi chapter for more information on formats for this transfer protocol. like the uar t , this interface has hardware requirements that limit the maximum speed that the ssi clock can run. this allows the ssi clock to be at most 1/12 the crystal frequency of the board running october 01, 2007 360 preliminary serial flash loader
the flash loader . since the host device is the master , the ssi on the flash loader device does not need to determine the clock as it is provided directly by the host. a.3 packet handling all communications, with the exception of the uar t auto-baud, are done via defined packets that are acknowledged (ack) or not acknowledged (nak) by the devices. the packets use the same format for receiving and sending packets, including the method used to acknowledge successful or unsuccessful reception of a packet. a.3.1 packet format all packets sent and received from the device use the following byte-packed format. struct { unsigned char ucsize; unsigned char ucchecksum; unsigned char data[]; }; ucsize the first byte received holds the total size of the transfer including the size and checksum bytes. ucchecksum this holds a simple checksum of the bytes in the data buf fer only . the algorithm is data[0]+data[1]++ data[ ucsize -3]. data this is the raw data intended for the device, which is formatted in some form of command interface. there should be ucsize C2 bytes of data provided in this buf fer to or from the device. a.3.2 sending packets the actual bytes of the packet can be sent individually or all at once; the only limitation is that commands that cause flash memory access should limit the download sizes to prevent losing bytes during flash programming. this limitation is discussed further in the section that describes the serial flash loader command, command_send_da t a (see command_send_da t a (0x24) on page 363 ). once the packet has been formatted correctly by the host, it should be sent out over the uar t or ssi interface. then the host should poll the uar t or ssi interface for the first non-zero data returned from the device. the first non-zero byte will either be an ack (0xcc) or a nak (0x33) byte from the device indicating the packet was received successfully (ack) or unsuccessfully (nak). this does not indicate that the actual contents of the command issued in the data portion of the packet were valid, just that the packet was received correctly . a.3.3 receiving packets the flash loader sends a packet of data in the same format that it receives a packet. the flash loader may transfer leading zero data before the first actual byte of data is sent out. the first non-zero byte is the size of the packet followed by a checksum byte, and finally followed by the data itself. there is no break in the data after the first non-zero byte is sent from the flash loader . once the device communicating with the flash loader receives all the bytes, it must either ack or nak the packet to indicate that the transmission was successful. the appropriate response after sending a nak to the flash loader is to resend the command that failed and request the data again. if needed, the host may send leading zeros before sending down the ack/nak signal to the flash loader , as the 361 october 01, 2007 preliminary lm3s600 microcontroller
flash loader only accepts the first non-zero data as a valid response. this zero padding is needed by the ssi interface in order to receive data to or from the flash loader . a.4 commands the next section defines the list of commands that can be sent to the flash loader . the first byte of the data should always be one of the defined commands, followed by data or parameters as determined by the command that is sent. a.4.1 command_ping (0x20) this command simply accepts the command and sets the global status to success. the format of the packet is as follows: byte[0] = 0x03; byte[1] = checksum(byte[2]); byte[2] = command_ping; the ping command has 3 bytes and the value for command_ping is 0x20 and the checksum of one byte is that same byte, making byte[1] also 0x20. since the ping command has no real return status, the receipt of an ack can be interpreted as a successful ping to the flash loader . a.4.2 command_get_st a tus (0x23) this command returns the status of the last command that was issued. t ypically , this command should be sent after every command to ensure that the previous command was successful or to properly respond to a failure. the command requires one byte in the data of the packet and should be followed by reading a packet with one byte of data that contains a status code. the last step is to ack or nak the received data so the flash loader knows that the data has been read. byte[0] = 0x03 byte[1] = checksum(byte[2]) byte[2] = command_get_status a.4.3 command_download (0x21) this command is sent to the flash loader to indicate where to store data and how many bytes will be sent by the command_send_data commands that follow . the command consists of two 32-bit values that are both transferred msb first. the first 32-bit value is the address to start programming data into, while the second is the 32-bit size of the data that will be sent. this command also triggers an erase of the full area to be programmed so this command takes longer than other commands. this results in a longer time to receive the ack/nak back from the board. this command should be followed by a command_get_status to ensure that the program address and program size are valid for the device running the flash loader . the format of the packet to send this command is a follows: byte[0] = 11 byte[1] = checksum(bytes[2:10]) byte[2] = command_download byte[3] = program address [31:24] byte[4] = program address [23:16] byte[5] = program address [15:8] byte[6] = program address [7:0] byte[7] = program size [31:24] october 01, 2007 362 preliminary serial flash loader
byte[8] = program size [23:16] byte[9] = program size [15:8] byte[10] = program size [7:0] a.4.4 command_send_da t a (0x24) this command should only follow a command_download command or another command_send_data command if more data is needed. consecutive send data commands automatically increment address and continue programming from the previous location. the caller should limit transfers of data to a maximum 8 bytes of packet data to allow the flash to program successfully and not overflow input buf fers of the serial interfaces. the command terminates programming once the number of bytes indicated by the command_download command has been received. each time this function is called it should be followed by a command_get_status to ensure that the data was successfully programmed into the flash. if the flash loader sends a nak to this command, the flash loader does not increment the current address to allow retransmission of the previous data. byte[0] = 11 byte[1] = checksum(bytes[2:10]) byte[2] = command_send_data byte[3] = data[0] byte[4] = data[1] byte[5] = data[2] byte[6] = data[3] byte[7] = data[4] byte[8] = data[5] byte[9] = data[6] byte[10] = data[7] a.4.5 command_run (0x22) this command is used to tell the flash loader to execute from the address passed as the parameter in this command. this command consists of a single 32-bit value that is interpreted as the address to execute. the 32-bit value is transmitted msb first and the flash loader responds with an ack signal back to the host device before actually executing the code at the given address. this allows the host to know that the command was received successfully and the code is now running. byte[0] = 7 byte[1] = checksum(bytes[2:6]) byte[2] = command_run byte[3] = execute address[31:24] byte[4] = execute address[23:16] byte[5] = execute address[15:8] byte[6] = execute address[7:0] a.4.6 command_reset (0x25) this command is used to tell the flash loader device to reset. this is useful when downloading a new image that overwrote the flash loader and wants to start from a full reset. unlike the command_run command, this allows the initial stack pointer to be read by the hardware and set up for the new code. it can also be used to reset the flash loader if a critical error occurs and the host device wants to restart communication with the flash loader . 363 october 01, 2007 preliminary lm3s600 microcontroller
byte[0] = 3 byte[1] = checksum(byte[2]) byte[2] = command_reset the flash loader responds with an ack signal back to the host device before actually executing the software reset to the device running the flash loader . this allows the host to know that the command was received successfully and the part will be reset. october 01, 2007 364 preliminary serial flash loader
b register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 system control base 0x400f .e000 did0, type ro, offset 0x000, reset - ver minor major pborctl, type r/w , offset 0x030, reset 0x0000.7ffd bor wt borior bor tim ldopctl, type r/w , offset 0x034, reset 0x0000.0000 v adj ris, type ro, offset 0x050, reset 0x0000.0000 pllfris borris ldoris mofris iofris clris plllris imc, type r/w , offset 0x054, reset 0x0000.0000 pllfim borim ldoim mofim iofim clim plllim misc, type r/w1c, offset 0x058, reset 0x0000.0000 bormis ldomis mofmis iofmis clmis plllmis resc, type r/w , offset 0x05c, reset - ext por bor wdt sw ldo rcc, type r/w , offset 0x060, reset 0x07a0.3ad1 usesysdiv sysdiv acg moscdis ioscdis moscver ioscver oscsrc xt al pll ver byp ass oen pwrdn pllcfg, type ro, offset 0x064, reset - r f od dslpclkcfg, type r/w , offset 0x144, reset 0x0780.0000 iosc clkvclr, type r/w , offset 0x150, reset 0x0000.0000 verclr ldoarst , type r/w , offset 0x160, reset 0x0000.0000 ldoarst did1, type ro, offset 0x004, reset - p ar tno f am ver qual rohs pkg temp dc0, type ro, offset 0x008, reset 0x001f .000f sramsz flashsz dc1, type ro, offset 0x010, reset 0x0000.309f jt ag swd swo wdt pll mpu minsysdiv dc2, type ro, offset 0x014, reset 0x0707.1013 timer0 timer1 timer2 comp0 comp1 comp2 uar t0 uar t1 ssi0 i2c0 365 october 01, 2007 preliminary lm3s600 microcontroller
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 dc3, type ro, offset 0x018, reset 0x3f00.7fc0 ccp0 ccp1 ccp2 ccp3 ccp4 ccp5 c0minus c0plus c0o c1minus c1plus c1o c2minus c2plus c2o dc4, type ro, offset 0x01c, reset 0x0000.001f gpioa gpiob gpioc gpiod gpioe rcgc0, type r/w , offset 0x100, reset 0x00000040 wdt scgc0, type r/w , offset 0x1 10, reset 0x00000040 wdt dcgc0, type r/w , offset 0x120, reset 0x00000040 wdt rcgc1, type r/w , offset 0x104, reset 0x00000000 timer0 timer1 timer2 comp0 comp1 comp2 uar t0 uar t1 ssi0 i2c0 scgc1, type r/w , offset 0x1 14, reset 0x00000000 timer0 timer1 timer2 comp0 comp1 comp2 uar t0 uar t1 ssi0 i2c0 dcgc1, type r/w , offset 0x124, reset 0x00000000 timer0 timer1 timer2 comp0 comp1 comp2 uar t0 uar t1 ssi0 i2c0 rcgc2, type r/w , offset 0x108, reset 0x00000000 gpioa gpiob gpioc gpiod gpioe scgc2, type r/w , offset 0x1 18, reset 0x00000000 gpioa gpiob gpioc gpiod gpioe dcgc2, type r/w , offset 0x128, reset 0x00000000 gpioa gpiob gpioc gpiod gpioe srcr0, type r/w , offset 0x040, reset 0x00000000 wdt srcr1, type r/w , offset 0x044, reset 0x00000000 timer0 timer1 timer2 comp0 comp1 comp2 uar t0 uar t1 ssi0 i2c0 srcr2, type r/w , offset 0x048, reset 0x00000000 gpioa gpiob gpioc gpiod gpioe internal memory flash control offset base 0x400f .d000 fma, type r/w , offset 0x000, reset 0x0000.0000 offset fmd, type r/w , offset 0x004, reset 0x0000.0000 da t a da t a october 01, 2007 366 preliminary register quick reference
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 fmc, type r/w , offset 0x008, reset 0x0000.0000 wrkey write erase merase comt fcris, type ro, offset 0x00c, reset 0x0000.0000 aris pris fcim, type r/w , offset 0x010, reset 0x0000.0000 amask pmask fcmisc, type r/w1c, offset 0x014, reset 0x0000.0000 amisc pmisc internal memory system control offset base 0x400f .e000 usecrl, type r/w , offset 0x140, reset 0x31 usec fmpre, type r/w , offset 0x130, reset 0x8000.ffff read_enable read_enable fmppe, type r/w , offset 0x134, reset 0x0000.ffff prog_enable prog_enable general-purpose input/outputs (gpios) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpioda t a, type r/w , offset 0x000, reset 0x0000.0000 da t a gpiodir, type r/w , offset 0x400, reset 0x0000.0000 dir gpiois, type r/w , offset 0x404, reset 0x0000.0000 is gpioibe, type r/w , offset 0x408, reset 0x0000.0000 ibe gpioiev , type r/w , offset 0x40c, reset 0x0000.0000 iev gpioim, type r/w , offset 0x410, reset 0x0000.0000 ime gpioris, type ro, offset 0x414, reset 0x0000.0000 ris gpiomis, type ro, offset 0x418, reset 0x0000.0000 mis 367 october 01, 2007 preliminary lm3s600 microcontroller
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 gpioicr, type w1c, offset 0x41c, reset 0x0000.0000 ic gpioafsel, type r/w , offset 0x420, reset - afsel gpiodr2r, type r/w , offset 0x500, reset 0x0000.00ff dr v2 gpiodr4r, type r/w , offset 0x504, reset 0x0000.0000 dr v4 gpiodr8r, type r/w , offset 0x508, reset 0x0000.0000 dr v8 gpioodr, type r/w , offset 0x50c, reset 0x0000.0000 ode gpiopur, type r/w , offset 0x510, reset 0x0000.00ff pue gpiopdr, type r/w , offset 0x514, reset 0x0000.0000 pde gpioslr, type r/w , offset 0x518, reset 0x0000.0000 srl gpioden, type r/w , offset 0x51c, reset 0x0000.00ff den gpioperiphid4, type ro, offset 0xfd0, reset 0x0000.0000 pid4 gpioperiphid5, type ro, offset 0xfd4, reset 0x0000.0000 pid5 gpioperiphid6, type ro, offset 0xfd8, reset 0x0000.0000 pid6 gpioperiphid7, type ro, offset 0xfdc, reset 0x0000.0000 pid7 gpioperiphid0, type ro, offset 0xfe0, reset 0x0000.0061 pid0 gpioperiphid1, type ro, offset 0xfe4, reset 0x0000.0000 pid1 gpioperiphid2, type ro, offset 0xfe8, reset 0x0000.0018 pid2 october 01, 2007 368 preliminary register quick reference
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 gpioperiphid3, type ro, offset 0xfec, reset 0x0000.0001 pid3 gpiopcellid0, type ro, offset 0xff0, reset 0x0000.000d cid0 gpiopcellid1, type ro, offset 0xff4, reset 0x0000.00f0 cid1 gpiopcellid2, type ro, offset 0xff8, reset 0x0000.0005 cid2 gpiopcellid3, type ro, offset 0xffc, reset 0x0000.00b1 cid3 general-purpose t imers t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 gptmcfg, type r/w , offset 0x000, reset 0x0000.0000 gptmcfg gptmt amr, type r/w , offset 0x004, reset 0x0000.0000 t amr t acmr t aams gptmtbmr, type r/w , offset 0x008, reset 0x0000.0000 tbmr tbcmr tbams gptmctl, type r/w , offset 0x00c, reset 0x0000.0000 t aen t ast all t aevent r tcen t aote t apwml tben tbst all tbevent tbote tbpwml gptmimr, type r/w , offset 0x018, reset 0x0000.0000 t a t oim camim caeim r tcim tbt oim cbmim cbeim gptmris, type ro, offset 0x01c, reset 0x0000.0000 t a t oris camris caeris r tcris tbt oris cbmris cberis gptmmis, type ro, offset 0x020, reset 0x0000.0000 t a t omis cammis caemis r tcmis tbt omis cbmmis cbemis gptmicr, type w1c, offset 0x024, reset 0x0000.0000 t a t ocint camcint caecint r tccint tbt ocint cbmcint cbecint gptmt ailr, type r/w , offset 0x028, reset 0x0000.ffff (16-bit mode) and 0xffff .ffff (32-bit mode) t ailrh t ailrl gptmtbilr, type r/w , offset 0x02c, reset 0x0000.ffff tbilrl gptmt ama tchr, type r/w , offset 0x030, reset 0x0000.ffff (16-bit mode) and 0xffff .ffff (32-bit mode) t amrh t amrl 369 october 01, 2007 preliminary lm3s600 microcontroller
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 gptmtbma tchr, type r/w , offset 0x034, reset 0x0000.ffff tbmrl gptmt apr, type r/w , offset 0x038, reset 0x0000.0000 t apsr gptmtbpr, type r/w , offset 0x03c, reset 0x0000.0000 tbpsr gptmt apmr, type r/w , offset 0x040, reset 0x0000.0000 t apsmr gptmtbpmr, type r/w , offset 0x044, reset 0x0000.0000 tbpsmr gptmt ar, type ro, offset 0x048, reset 0x0000.ffff (16-bit mode) and 0xffff .ffff (32-bit mode) t arh t arl gptmtbr, type ro, offset 0x04c, reset 0x0000.ffff tbrl w atchdog t imer base 0x4000.0000 wdtload, type r/w , offset 0x000, reset 0xffff .ffff wdtload wdtload wdtv alue, type ro, offset 0x004, reset 0xffff .ffff wdtv alue wdtv alue wdtctl, type r/w , offset 0x008, reset 0x0000.0000 inten resen wdticr, type wo, offset 0x00c, reset - wdtintclr wdtintclr wdtris, type ro, offset 0x010, reset 0x0000.0000 wdtris wdtmis, type ro, offset 0x014, reset 0x0000.0000 wdtmis wdttest , type r/w , offset 0x418, reset 0x0000.0000 st all wdtlock, type r/w , offset 0xc00, reset 0x0000.0000 wdtlock wdtlock wdtperiphid4, type ro, offset 0xfd0, reset 0x0000.0000 pid4 wdtperiphid5, type ro, offset 0xfd4, reset 0x0000.0000 pid5 october 01, 2007 370 preliminary register quick reference
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 wdtperiphid6, type ro, offset 0xfd8, reset 0x0000.0000 pid6 wdtperiphid7, type ro, offset 0xfdc, reset 0x0000.0000 pid7 wdtperiphid0, type ro, offset 0xfe0, reset 0x0000.0005 pid0 wdtperiphid1, type ro, offset 0xfe4, reset 0x0000.0018 pid1 wdtperiphid2, type ro, offset 0xfe8, reset 0x0000.0018 pid2 wdtperiphid3, type ro, offset 0xfec, reset 0x0000.0001 pid3 wdtpcellid0, type ro, offset 0xff0, reset 0x0000.000d cid0 wdtpcellid1, type ro, offset 0xff4, reset 0x0000.00f0 cid1 wdtpcellid2, type ro, offset 0xff8, reset 0x0000.0005 cid2 wdtpcellid3, type ro, offset 0xffc, reset 0x0000.00b1 cid3 universal asynchronous receivers/t ransmitters (uart s) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 uartdr, type r/w , offset 0x000, reset 0x0000.0000 da t a fe pe be oe uartrsr/uartecr, type ro, offset 0x004, reset 0x0000.0000 fe pe be oe uartrsr/uartecr, type wo, offset 0x004, reset 0x0000.0000 da t a uartfr, type ro, offset 0x018, reset 0x0000.0090 busy rxfe txff rxff txfe uartibrd, type r/w , offset 0x024, reset 0x0000.0000 divint uartfbrd, type r/w , offset 0x028, reset 0x0000.0000 divfrac 371 october 01, 2007 preliminary lm3s600 microcontroller
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 uartlcrh, type r/w , offset 0x02c, reset 0x0000.0000 brk pen eps stp2 fen wlen sps uartctl, type r/w , offset 0x030, reset 0x0000.0300 uar ten lbe txe rxe uartifls, type r/w , offset 0x034, reset 0x0000.0012 txiflsel rxiflsel uartim, type r/w , offset 0x038, reset 0x0000.0000 rxim txim r tim feim peim beim oeim uartris, type ro, offset 0x03c, reset 0x0000.000f rxris txris r tris feris peris beris oeris uartmis, type ro, offset 0x040, reset 0x0000.0000 rxmis txmis r tmis femis pemis bemis oemis uarticr, type w1c, offset 0x044, reset 0x0000.0000 rxic txic r tic feic peic beic oeic uartperiphid4, type ro, offset 0xfd0, reset 0x0000.0000 pid4 uartperiphid5, type ro, offset 0xfd4, reset 0x0000.0000 pid5 uartperiphid6, type ro, offset 0xfd8, reset 0x0000.0000 pid6 uartperiphid7, type ro, offset 0xfdc, reset 0x0000.0000 pid7 uartperiphid0, type ro, offset 0xfe0, reset 0x0000.001 1 pid0 uartperiphid1, type ro, offset 0xfe4, reset 0x0000.0000 pid1 uartperiphid2, type ro, offset 0xfe8, reset 0x0000.0018 pid2 uartperiphid3, type ro, offset 0xfec, reset 0x0000.0001 pid3 uartpcellid0, type ro, offset 0xff0, reset 0x0000.000d cid0 uartpcellid1, type ro, offset 0xff4, reset 0x0000.00f0 cid1 october 01, 2007 372 preliminary register quick reference
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 uartpcellid2, type ro, offset 0xff8, reset 0x0000.0005 cid2 uartpcellid3, type ro, offset 0xffc, reset 0x0000.00b1 cid3 synchronous serial interface (ssi) ssi0 base: 0x4000.8000 ssicr0, type r/w , offset 0x000, reset 0x0000.0000 dss frf spo sph scr ssicr1, type r/w , offset 0x004, reset 0x0000.0000 lbm sse ms sod ssidr, type r/w , offset 0x008, reset 0x0000.0000 da t a ssisr, type ro, offset 0x00c, reset 0x0000.0003 tfe tnf rne rff bsy ssicpsr, type r/w , offset 0x010, reset 0x0000.0000 cpsdvsr ssiim, type r/w , offset 0x014, reset 0x0000.0000 rorim r tim rxim txim ssiris, type ro, offset 0x018, reset 0x0000.0008 rorris r tris rxris txris ssimis, type ro, offset 0x01c, reset 0x0000.0000 rormis r tmis rxmis txmis ssiicr, type w1c, offset 0x020, reset 0x0000.0000 roric r tic ssiperiphid4, type ro, offset 0xfd0, reset 0x0000.0000 pid4 ssiperiphid5, type ro, offset 0xfd4, reset 0x0000.0000 pid5 ssiperiphid6, type ro, offset 0xfd8, reset 0x0000.0000 pid6 ssiperiphid7, type ro, offset 0xfdc, reset 0x0000.0000 pid7 ssiperiphid0, type ro, offset 0xfe0, reset 0x0000.0022 pid0 ssiperiphid1, type ro, offset 0xfe4, reset 0x0000.0000 pid1 373 october 01, 2007 preliminary lm3s600 microcontroller
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 ssiperiphid2, type ro, offset 0xfe8, reset 0x0000.0018 pid2 ssiperiphid3, type ro, offset 0xfec, reset 0x0000.0001 pid3 ssipcellid0, type ro, offset 0xff0, reset 0x0000.000d cid0 ssipcellid1, type ro, offset 0xff4, reset 0x0000.00f0 cid1 ssipcellid2, type ro, offset 0xff8, reset 0x0000.0005 cid2 ssipcellid3, type ro, offset 0xffc, reset 0x0000.00b1 cid3 inter-integrated circuit (i 2 c) interface i 2 c master i2c master 0 base: 0x4002.0000 i2cmsa, type r/w , offset 0x000, reset 0x0000.0000 r/s sa i2cmcs, type ro, offset 0x004, reset 0x0000.0000 busy error adrack da t ack arblst idle busbsy i2cmcs, type wo, offset 0x004, reset 0x0000.0000 run st ar t st op ack i2cmdr, type r/w , offset 0x008, reset 0x0000.0000 da t a i2cmtpr, type r/w , offset 0x00c, reset 0x0000.0001 tpr i2cmimr, type r/w , offset 0x010, reset 0x0000.0000 im i2cmris, type ro, offset 0x014, reset 0x0000.0000 ris i2cmmis, type ro, offset 0x018, reset 0x0000.0000 mis i2cmicr, type wo, offset 0x01c, reset 0x0000.0000 ic i2cmcr, type r/w , offset 0x020, reset 0x0000.0000 lpbk mfe sfe inter-integrated circuit (i 2 c) interface october 01, 2007 374 preliminary register quick reference
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 i 2 c slave i2c slave 0 base: 0x4002.0800 i2csoar, type r/w , offset 0x000, reset 0x0000.0000 oar i2cscsr, type ro, offset 0x004, reset 0x0000.0000 rreq treq fbr i2cscsr, type wo, offset 0x004, reset 0x0000.0000 da i2csdr, type r/w , offset 0x008, reset 0x0000.0000 da t a i2csimr, type r/w , offset 0x00c, reset 0x0000.0000 im i2csris, type ro, offset 0x010, reset 0x0000.0000 ris i2csmis, type ro, offset 0x014, reset 0x0000.0000 mis i2csicr, type wo, offset 0x018, reset 0x0000.0000 ic analog comparators base 0x4003.c000 acmis, type r/w1c, offset 0x00, reset 0x0000.0000 in0 in1 in2 acris, type ro, offset 0x04, reset 0x0000.0000 in0 in1 in2 acinten, type r/w , offset 0x08, reset 0x0000.0000 in0 in1 in2 acrefctl, type r/w , offset 0x10, reset 0x0000.0000 vref rng en acst a t0, type ro, offset 0x20, reset 0x0000.0000 ov al acst a t1, type ro, offset 0x40, reset 0x0000.0000 ov al acst a t2, type ro, offset 0x60, reset 0x0000.0000 ov al acctl0, type r/w , offset 0x24, reset 0x0000.0000 cinv isen isl v al asrcp 375 october 01, 2007 preliminary lm3s600 microcontroller
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 acctl1, type r/w , offset 0x44, reset 0x0000.0000 cinv isen isl v al asrcp acctl2, type r/w , offset 0x64, reset 0x0000.0000 cinv isen isl v al asrcp october 01, 2007 376 preliminary register quick reference
c ordering and contact information c.1 ordering information t able c-1. part ordering information description orderable part number stellaris ? lm3s600 microcontroller lm3s600-iqn50 stellaris ? lm3s600 microcontroller lm3s600-iqn50(t) c.2 kits the luminary micro stellaris ? family provides the hardware and software tools that engineers need to begin development quickly . reference design kits accelerate product development by providing ready-to-run hardware, and comprehensive documentation including hardware design files: http://www .luminarymicro.com/products/reference_design_kits/ evaluation kits provide a low-cost and ef fective means of evaluating stellaris ? microcontrollers before purchase: http://www .luminarymicro.com/products/evaluation_kits/ development kits provide you with all the tools you need to develop and prototype embedded applications right out of the box: http://www .luminarymicro.com/products/boards.html see the luminary micro website for the latest tools available or ask your luminary micro distributor . c.3 company information luminary micro, inc. designs, markets, and sells arm cortex-m3-based microcontrollers (mcus). austin, t exas-based luminary micro is the lead partner for the cortex-m3 processor , delivering the world's first silicon implementation of the cortex-m3 processor . luminary micro's introduction of the 377 october 01, 2007 preliminary lm3s600 microcontroller l m 3 s n n n n C g p p s s C r r m part number t emperature package speed revision shipping medium i = -40 c to 85 c t = t ape-and-reel omitted = default shipping (tray or tube) omitted = default to current shipping revision a 0 = first all-layer mask a 1 = metal layers update to a0 a 2 = metal layers update to a1 b 0 = second all-layer mask revision rn = 28-pin soic qn = 48-pin lqfp qc = 100-pin lqfp 20 = 20 mhz 25 = 25 mhz 50 = 50 mhz
stellaris? family of products provides 32-bit performance for the same price as current 8- and 16-bit microcontroller designs. with entry-level pricing at $1.00 for an arm technology-based mcu, luminary micro's stellaris product line allows for standardization that eliminates future architectural upgrades or software tool changes. luminary micro, inc. 108 wild basin, suite 350 austin, tx 78746 main: +1-512-279-8800 fax: +1-512-279-8879 http://www .luminarymicro.com sales@luminarymicro.com c.4 support information for support on luminary micro products, contact: support@luminarymicro.com +1-512-279-8800, ext. 3 october 01, 2007 378 preliminary ordering and contact information

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